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Local Group Policy
I have an issue with local group policies being applied and enforced. Not sure what their source is but if removed from local group policy editor and another policy with different settings are applied. The issue remains the same. for e.g.AhmedSHMKFeb 10, 2025Brass Contributor20Views0likes1CommentBPA Errors: DNS can't resolve GC, Kerberos, PDC Resource Record, etc.
Hello, I've been poking around this for hours now and could use another set of eyes. This server has been the PDC for quite some time but I discovered the last people that managed this place, didn't demote the old 2008R2 server (thankfully it still existed virtualized). So I was able to do a graceful demotion of that and removed it from the domain. I'm now trying to resolve some other errors in that come up in the BPA scan... All reference DNS and I just can't figure this out. I've been beating head against the wall trying to understand what's happening, This is MS Server Standard 2022 only 1 DC and DNS. (yeah I know, don't get me started, but it's a really small office)... Would love some suggestions. Thanks!BenTheITGuyFeb 09, 2025Copper Contributor58Views1like5CommentsDoes my Intel(R) Core(TM) i7-7700 CPU @ 3.60GHz support Windows Server 2025
I have checked the hardware requirements for Windows server here. On the same webpage, it is proposed that Coreinfo be used to verify the capabilities of the CPU. From all the requirements I do not see in my CPU list the following ones (Coreinfo output attached at the end): Support for NX and DEP -> DEP does not appear in the list Support for Second Level Address Translation (EPT or NPT) -> I do not recognize any of these in the list. I've checked another machine currently running Windows Server 2019, which mounts an Intel(R) Xeon(R) E-2234 CPU @ 3.60GHz (Coreinfo output attached at the end). Running the Coreinfo on that machine produced an output where I could not find any of the two in the previous list (NX and DEP; Second Level Address Translation). Is there another way of checking these requirements? Are they satisfied with the Intel Core i7-7700? Core info for Intel(R) Core(TM) i7-7700 CPU @ 3.60GHz Coreinfo v3.6 - Dump information on system CPU and memory topology Copyright (C) 2008-2022 Mark Russinovich Sysinternals - www.sysinternals.com Intel(R) Core(TM) i7-7700 CPU @ 3.60GHz Intel64 Family 6 Model 158 Stepping 9, GenuineIntel Microcode signature: 000000B4 HTT * Hyperthreading enabled CET - Supports Control Flow Enforcement Technology Kernel CET - Kernel-mode CET Enabled User CET - User-mode CET Allowed HYPERVISOR * Hypervisor is present VMX - Supports Intel hardware-assisted virtualization SVM - Supports AMD hardware-assisted virtualization X64 * Supports 64-bit mode SMX - Supports Intel trusted execution SKINIT - Supports AMD SKINIT SGX - Supports Intel SGX NX * Supports no-execute page protection SMEP * Supports Supervisor Mode Execution Prevention SMAP * Supports Supervisor Mode Access Prevention PAGE1GB * Supports 1 GB large pages PAE * Supports > 32-bit physical addresses PAT * Supports Page Attribute Table PSE * Supports 4 MB pages PSE36 * Supports > 32-bit address 4 MB pages PGE * Supports global bit in page tables SS * Supports bus snooping for cache operations VME * Supports Virtual-8086 mode RDWRFSGSBASE * Supports direct GS/FS base access FPU * Implements i387 floating point instructions MMX * Supports MMX instruction set MMXEXT - Implements AMD MMX extensions 3DNOW - Supports 3DNow! instructions 3DNOWEXT - Supports 3DNow! extension instructions SSE * Supports Streaming SIMD Extensions SSE2 * Supports Streaming SIMD Extensions 2 SSE3 * Supports Streaming SIMD Extensions 3 SSSE3 * Supports Supplemental SIMD Extensions 3 SSE4a - Supports Streaming SIMDR Extensions 4a SSE4.1 * Supports Streaming SIMD Extensions 4.1 SSE4.2 * Supports Streaming SIMD Extensions 4.2 AES * Supports AES extensions AVX * Supports AVX instruction extensions AVX2 * Supports AVX2 instruction extensions AVX-512-F - Supports AVX-512 Foundation instructions AVX-512-DQ - Supports AVX-512 double and quadword instructions AVX-512-IFAMA - Supports AVX-512 integer Fused multiply-add instructions AVX-512-PF - Supports AVX-512 prefetch instructions AVX-512-ER - Supports AVX-512 exponential and reciprocal instructions AVX-512-CD - Supports AVX-512 conflict detection instructions AVX-512-BW - Supports AVX-512 byte and word instructions AVX-512-VL - Supports AVX-512 vector length instructions FMA * Supports FMA extensions using YMM state MSR * Implements RDMSR/WRMSR instructions MTRR * Supports Memory Type Range Registers XSAVE * Supports XSAVE/XRSTOR instructions OSXSAVE * Supports XSETBV/XGETBV instructions RDRAND * Supports RDRAND instruction RDSEED * Supports RDSEED instruction CMOV * Supports CMOVcc instruction CLFSH * Supports CLFLUSH instruction CX8 * Supports compare and exchange 8-byte instructions CX16 * Supports CMPXCHG16B instruction BMI1 * Supports bit manipulation extensions 1 BMI2 * Supports bit manipulation extensions 2 ADX * Supports ADCX/ADOX instructions DCA - Supports prefetch from memory-mapped device F16C * Supports half-precision instruction FXSR * Supports FXSAVE/FXSTOR instructions FFXSR - Supports optimized FXSAVE/FSRSTOR instruction MONITOR - Supports MONITOR and MWAIT instructions MOVBE * Supports MOVBE instruction ERMSB * Supports Enhanced REP MOVSB/STOSB PCLMULDQ * Supports PCLMULDQ instruction POPCNT * Supports POPCNT instruction LZCNT * Supports LZCNT instruction SEP * Supports fast system call instructions LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode HLE * Supports Hardware Lock Elision instructions RTM * Supports Restricted Transactional Memory instructions DE * Supports I/O breakpoints including CR4.DE DTES64 * Can write history of 64-bit branch addresses DS * Implements memory-resident debug buffer DS-CPL - Supports Debug Store feature with CPL PCID * Supports PCIDs and settable CR4.PCIDE INVPCID * Supports INVPCID instruction PDCM * Supports Performance Capabilities MSR RDTSCP * Supports RDTSCP instruction TSC * Supports RDTSC instruction TSC-DEADLINE - Local APIC supports one-shot deadline timer TSC-INVARIANT * TSC runs at constant rate xTPR * Supports disabling task priority messages EIST * Supports Enhanced Intel Speedstep ACPI * Implements MSR for power management TM * Implements thermal monitor circuitry TM2 * Implements Thermal Monitor 2 control APIC * Implements software-accessible local APIC x2APIC - Supports x2APIC CNXT-ID - L1 data cache mode adaptive or BIOS MCE * Supports Machine Check, INT18 and CR4.MCE MCA * Implements Machine Check Architecture PBE * Supports use of FERR#/PBE# pin PSN - Implements 96-bit processor serial number PREFETCHW * Supports PREFETCHW instruction Maximum implemented CPUID leaves: 00000016 (Basic), 80000008 (Extended). Maximum implemented address width: 48 bits (virtual), 39 bits (physical). Processor signature: 000906E9 Logical to Physical Processor Map: **------ Physical Processor 0 (Hyperthreaded) --**---- Physical Processor 1 (Hyperthreaded) ----**-- Physical Processor 2 (Hyperthreaded) ------** Physical Processor 3 (Hyperthreaded) Logical Processor to Socket Map: ******** Socket 0 Logical Processor to NUMA Node Map: ******** NUMA Node 0 No NUMA nodes. Logical Processor to Cache Map: **------ Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 **------ Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 **------ Unified Cache 0, Level 2, 256 KB, Assoc 4, LineSize 64 ******** Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64 --**---- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64 --**---- Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64 --**---- Unified Cache 2, Level 2, 256 KB, Assoc 4, LineSize 64 ----**-- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64 ----**-- Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64 ----**-- Unified Cache 3, Level 2, 256 KB, Assoc 4, LineSize 64 ------** Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64 ------** Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64 ------** Unified Cache 4, Level 2, 256 KB, Assoc 4, LineSize 64 Logical Processor to Group Map: ******** Group 0 Core info for Intel(R) Xeon(R) E-2234 CPU @ 3.60GHz Coreinfo v3.6 - Dump information on system CPU and memory topology Copyright (C) 2008-2022 Mark Russinovich Sysinternals - www.sysinternals.com Intel(R) Xeon(R) E-2234 CPU @ 3.60GHz Intel64 Family 6 Model 158 Stepping 10, GenuineIntel Microcode signature: 000000DE HTT * Hyperthreading enabled Error loading driver: Se ha bloqueado la descarga de este controlador Querying CET support requires admin rights HYPERVISOR * Hypervisor is present VMX - Supports Intel hardware-assisted virtualization SVM - Supports AMD hardware-assisted virtualization X64 * Supports 64-bit mode SMX - Supports Intel trusted execution SKINIT - Supports AMD SKINIT SGX - Supports Intel SGX NX * Supports no-execute page protection SMEP * Supports Supervisor Mode Execution Prevention SMAP * Supports Supervisor Mode Access Prevention PAGE1GB * Supports 1 GB large pages PAE * Supports > 32-bit physical addresses PAT * Supports Page Attribute Table PSE * Supports 4 MB pages PSE36 * Supports > 32-bit address 4 MB pages PGE * Supports global bit in page tables SS * Supports bus snooping for cache operations VME * Supports Virtual-8086 mode RDWRFSGSBASE * Supports direct GS/FS base access FPU * Implements i387 floating point instructions MMX * Supports MMX instruction set MMXEXT - Implements AMD MMX extensions 3DNOW - Supports 3DNow! instructions 3DNOWEXT - Supports 3DNow! extension instructions SSE * Supports Streaming SIMD Extensions SSE2 * Supports Streaming SIMD Extensions 2 SSE3 * Supports Streaming SIMD Extensions 3 SSSE3 * Supports Supplemental SIMD Extensions 3 SSE4a - Supports Streaming SIMDR Extensions 4a SSE4.1 * Supports Streaming SIMD Extensions 4.1 SSE4.2 * Supports Streaming SIMD Extensions 4.2 AES * Supports AES extensions AVX * Supports AVX instruction extensions AVX2 * Supports AVX2 instruction extensions AVX-512-F - Supports AVX-512 Foundation instructions AVX-512-DQ - Supports AVX-512 double and quadword instructions AVX-512-IFAMA - Supports AVX-512 integer Fused multiply-add instructions AVX-512-PF - Supports AVX-512 prefetch instructions AVX-512-ER - Supports AVX-512 exponential and reciprocal instructions AVX-512-CD - Supports AVX-512 conflict detection instructions AVX-512-BW - Supports AVX-512 byte and word instructions AVX-512-VL - Supports AVX-512 vector length instructions FMA * Supports FMA extensions using YMM state MSR * Implements RDMSR/WRMSR instructions MTRR * Supports Memory Type Range Registers XSAVE * Supports XSAVE/XRSTOR instructions OSXSAVE * Supports XSETBV/XGETBV instructions RDRAND * Supports RDRAND instruction RDSEED * Supports RDSEED instruction CMOV * Supports CMOVcc instruction CLFSH * Supports CLFLUSH instruction CX8 * Supports compare and exchange 8-byte instructions CX16 * Supports CMPXCHG16B instruction BMI1 * Supports bit manipulation extensions 1 BMI2 * Supports bit manipulation extensions 2 ADX * Supports ADCX/ADOX instructions DCA - Supports prefetch from memory-mapped device F16C * Supports half-precision instruction FXSR * Supports FXSAVE/FXSTOR instructions FFXSR - Supports optimized FXSAVE/FSRSTOR instruction MONITOR - Supports MONITOR and MWAIT instructions MOVBE * Supports MOVBE instruction ERMSB * Supports Enhanced REP MOVSB/STOSB PCLMULDQ * Supports PCLMULDQ instruction POPCNT * Supports POPCNT instruction LZCNT * Supports LZCNT instruction SEP * Supports fast system call instructions LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode HLE * Supports Hardware Lock Elision instructions RTM * Supports Restricted Transactional Memory instructions DE * Supports I/O breakpoints including CR4.DE DTES64 * Can write history of 64-bit branch addresses DS * Implements memory-resident debug buffer DS-CPL - Supports Debug Store feature with CPL PCID * Supports PCIDs and settable CR4.PCIDE INVPCID * Supports INVPCID instruction PDCM * Supports Performance Capabilities MSR RDTSCP * Supports RDTSCP instruction TSC * Supports RDTSC instruction TSC-DEADLINE - Local APIC supports one-shot deadline timer TSC-INVARIANT * TSC runs at constant rate xTPR * Supports disabling task priority messages EIST * Supports Enhanced Intel Speedstep ACPI * Implements MSR for power management TM * Implements thermal monitor circuitry TM2 * Implements Thermal Monitor 2 control APIC * Implements software-accessible local APIC x2APIC * Supports x2APIC CNXT-ID - L1 data cache mode adaptive or BIOS MCE * Supports Machine Check, INT18 and CR4.MCE MCA * Implements Machine Check Architecture PBE * Supports use of FERR#/PBE# pin PSN - Implements 96-bit processor serial number PREFETCHW * Supports PREFETCHW instruction Maximum implemented CPUID leaves: 00000016 (Basic), 80000008 (Extended). Maximum implemented address width: 48 bits (virtual), 39 bits (physical). Processor signature: 000906EA Logical to Physical Processor Map: **------ Physical Processor 0 (Hyperthreaded) --**---- Physical Processor 1 (Hyperthreaded) ----**-- Physical Processor 2 (Hyperthreaded) ------** Physical Processor 3 (Hyperthreaded) Logical Processor to Socket Map: ******** Socket 0 Logical Processor to NUMA Node Map: ******** NUMA Node 0 No NUMA nodes. Logical Processor to Cache Map: **------ Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 **------ Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 **------ Unified Cache 0, Level 2, 256 KB, Assoc 4, LineSize 64 ******** Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64 --**---- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64 --**---- Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64 --**---- Unified Cache 2, Level 2, 256 KB, Assoc 4, LineSize 64 ----**-- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64 ----**-- Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64 ----**-- Unified Cache 3, Level 2, 256 KB, Assoc 4, LineSize 64 ------** Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64 ------** Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64 ------** Unified Cache 4, Level 2, 256 KB, Assoc 4, LineSize 64 Logical Processor to Group Map: ******** Group 0apalomerFeb 04, 2025Copper Contributor47Views0likes1CommentGroup Policy object did not apply because failed error code:0x80070709 The printer name is invalid
Hi Everyone, I have a few AVD pools where we publish an app for users to access. Users report that printers are not being mapped after login. We use GPP user side to map printers and set as default. Many a times we see these events logged: VALUE>The printer name is invalid.</VALUE></PROPERTY>-</INSTANCE> Event ID 4098 is logged in the Application Log: Log Name: Application Source: Group Policy Printers Date: <DateTime> Event ID: 4098 Task Category: (2) Level: Warning Keywords: Classic User: SYSTEM Computer: server.fabrikam.com Description: The user 'HP Printer' preference item in the 'Define Printers {XXX-XXXX-XXXX-XXXX-XXXXXXXXXXXX}' Group Policy object did not apply because it failed with error code '0x80070709 The printer name is invalid.' This error was suppressed. For this one I found this KB which is really not helpful since there is no possible solution as the client is a AVD VM and used by many users at the same time. VALUE> No printers were found.' VALUE></PROPERTY>-</INSTANCE> Event ID 4098 is logged in the Application Log: Log Name: Application Source: Group Policy Printers Date: <DateTime> Event ID: 4098 Task Category: (2) Level: Warning Keywords: Classic User: SYSTEM Computer: server.fabrikam.com Description: The user 'Accounts - Main Printer' preference item in the 'Printers - Global {zzzzzzzzzzzzzzzzzzzzz}' Group Policy Object did not apply because it failed with error code '0x80070bc4 No printers were found.' This error was suppressed. VALUE>The specified printer has been deleted.</VALUE></PROPERTY>-</INSTANCE> Event ID 4098 is logged in the Application Log: Log Name: Application Source: Group Policy Printers Date: <DateTime> Event ID: 4098 Task Category: (2) Level: Warning Keywords: Classic User: SYSTEM Computer: server.fabrikam.com Description: The user 'Sales-Printer' preference item in the 'Printers - Global {zzzzzzzzzzzzzzzzzzzzz}' Group Policy Object did not apply because it failed with error code '0x80070771 The specified printer has been deleted.' This error was suppressed. No KB's or posts out there to help with these 2 errors. Really need assistance and printers are not being mapped on first logon, users need to come out of AVD and go back and relaunch the app to see the printers mapped. This is the same case with our internal app or Notepad. Thanks, MDolinhasJan 28, 2025Brass Contributor802Views0likes2Comments2025-01 Cumulative Update for Windows Server 2019 KB5050008 Causing Slow Performance and Freezing
We had this same problem back in August with the 2024-08 Cumulative Update for Windows Server 2019 KB5041578, slow performance and freezing. Here we go again with KB5050008. Remote Desktop does not respond. It freezes up for minutes. We have SQL Server and Terminal Server on this Windows Server 2019 and people can't access it through Remote Desktop. I had to uninstall KB5050008. The server went back to normal. I don't a repeat of this with every Windows Server update. Please advise.Michael2000Jan 26, 2025Copper Contributor1.4KViews0likes2CommentsWindows Server 2025 Desktop Experience: Hyper-V cannot be installed
I have a lab with various Servers running Windows Server 2025. Some of them are installed without Desktop Experience, some with. Aside from Desktop Experience, the VMs and the operating are configured the same way using automated setup scripts. I exposed the VirtualizationExtensions for all VMs on the host using Set-VMProcessor -ExposeVirtualizationExtensions $true. Moreover, I configured all VMs to use static memory assignment. However, when I try to install Hyper-V on Windows Servers 2025 with Desktop Experience, I receive the error Hyper-V cannot be installed because virtualization support is not enabled in the BIOS. The issue occurs without any updates installed as well as with KB5050009 (2025-01 Cumulative Update for Microsoft server operating system 24H2 for x64 based Systems) installed. On machines without Desktop Experience, Hyper-V can be installed without any issues. As a side note, on VMs using Windows 11 24H2 on the same host, I can install Hyper-V without any issues.RokoryJan 23, 2025Brass Contributor205Views0likes4CommentsASCHI cluster different RAM amounts per node
is it a supported model for ASHCI to have 1 node in a cluster to have different amounts of RAM? i appreciate that you can specify preferred owners, and possible owners on VMs, to restrict/ allow VMs to go to specific hosts, and understand that under normal circumstances you probably wouldnt want to have hosts with different amounts of RAM to circumvent over provisioning and then getting into difficulties upon loosing hosts, but am looking at making one of my ASHCI hosts a SQL server, i dont want to remove it from the cluster due to impacting storage, but need to increase the RAM, and if i can do it to just a single host id prefer that.chrisbirleyJan 21, 2025Copper Contributor22Views0likes3CommentsCreating a test environment similar to prod - how to license?
Hi, We want to create a test environment to avoid "system wide" settings deploy to production without testing them first (e.g. Kerberos Enforcement or Entra Sync Settings) We would use Windows Trial licenses and Entra Connect to connect to a Testtenant. How must we license this test environment to be compliant with MS licensing? Some say it's Trial and not production "you do not have to". Others say we need to license "like Prod". Can anyone (preferably a Microsoft employee) help with this question? BR StephanStephanGeeJan 21, 2025Steel Contributor52Views1like2CommentsASHCI cluster with different RAM amounts
been looking through server requirements and things, and i cant see a definitive answer of whether i need to have the same amount of RAM per ASHCI host. i appreciate it may not be best practice due to failing over VMs within the cluster, and being in a position where you over provision RAM and could end up in a sticky situation, but given that you can not only set preferred owners, but also have the ability to set possible owners, you should be able to account for that. tldr: ASHCI cluster can i have have one node with 4TB of RAM and 5 nodes with 2TB of RAMchrisbirleyJan 21, 2025Copper Contributor14Views0likes1Comment
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