Come join Microsoft in the Design Infrastructure Alley
Published Jul 06 2022 08:49 AM 2,365 Views

By: Richard Paw, Principal Program Manager, Azure HPC + AI


Join us at our booth (1252) in the Design Infrastructure Alley to meet experts from Microsoft, Intel, and NetApp. Come and find out how we’ve collaborated to create an optimized environment for chip development on the cloud.  


Booth Mini-Theater

Visit our mini-theater to hear from speakers from industry partners including ANSYS, Cadence, Intel, NetApp, Siemens EDA, and Synopsys.  



Sessions you don’t want to miss  

Design on Cloud Theater - Architectural advantages of AMD Milan-X in Azure HBv3 for Logic Simulation 

Monday, July 11 | 10:30AM-11:15AM PT 

Philip Steinke, Fellow, AMD 

Verification consumes the majority of time and compute resources for chip development. For digital designs, logic simulation is often the largest component. AMD’s recently launched 3rd-gen EPYC processor with 3D V-Cache Technology (available now on Azure HBv3 VMs) features architectural elements that complement logic simulation and improve the performance of logic simulation. Join Philip Steinke as he discusses how these microprocessor architectural features combined with the system level architecture of the Microsoft Azure HBv3 hardware affects this workload, the advantages these features bring to logic simulation, and how AMD leverages these advantages for their silicon development. 


Intel Foundry Services (Booth 2325) – Partnering on the future of semiconductor manufacturing 

Monday, July 11 | 1:00AM-1:20AM PT 

Richard Paw, Director, Semiconductor and EDA, Microsoft Azure 

Intel and Microsoft have a long history of collaboration that stretches back decades. In recent years, the two companies worked together to introduce EDA centric cloud compute such as the FX series on Azure for semiconductor design, worked with the EDA industry to better take advantage of the cloud, and enabled secure cloud-based semiconductor development. Through the IFS Cloud Alliance Program, the two companies will continue to innovate on expanded best practices and capabilities for RTL through silicon development.  


Siemens EDA (Booth 2521) – “Design Time to Market Leveraging Innovations with Calibre nmDRC, on AMD  3rd-gen EPYC in the Microsoft Azure Cloud” 

Wednesday, July 13th | 11:00-11:15 
Andy Chan,  Director,  Azure Global Solutions, Semiconductor/EDA/CAE 
Philip Steinke, Fellow, AMD 
Michael White, Sr. Director, Physical Verification Product Management, Siemens 

As design complexity increases and compute requirements grows node to node, customers need to be able to process more workloads in the same time. Collaboration between Siemens EDA, AMD, and Microsoft results in innovations  for Calibre to better leverage AMD 3rd-gen EPYC ™ process at the large scale provided by Microsoft Azure. 

Ansys (Booth 1539) – Using Azure Cloud to Rapidly Simulate Designs in Ansys HFSS 

Monday, July 11 | 3:00PM-3:30PM PT 

Andy Chan, Director, Azure Global Solutions, Microsoft Azure 

Andy Chan will be at the Ansys booth as he discusses how Microsoft Azure and Ansys collaborated to enable HFSS to successfully simulate a full IC by scaling on the cloud. 


Ansys (Marriott Marquis Hotel) – Designing 3D-ICs in a 2D World 

Tuesday, July 12 | 7:00AM-9:00AM PT 

Chip Stratakos, Sr. Director, Silicon Design, Microsoft Azure 

Chip Stratakos will join other industry experts to discuss their experience with adopting 2.5D/3D-IC manufacturing for standard semiconductor products and bespoke silicon solutions.  


Design on Cloud Theater - Unleashing Full Analog Design and Simulation Environment on Optimized Cloud 

Tuesday, July 12 | 1:30PM-2:15PM PT 

Teng-Kiat Lee, Technical Marketing Director, Synopsys  
Richard Paw, Director, Semiconductor and EDA, Microsoft Azure 
Simon Rance, Vice President of Marketing, Cliosoft 

Synopsys Custom Compiler and PrimeSim are able to scale beyond what was previous possible to develop and analyze designs previously too large to process. Synopsys achieved this by leveraging Cliosoft to manage the analog design data and scaling on Azure to utilize GPUs to enable simulations at greater scale. 


Design on Cloud Training – Azure  

Wednesday, July 13 | 10:15AM-1:15PM PT 

This session will cover how customers can bring chip development software to the Azure cloud. We will cover the advantages and disadvantages, issues around migrating data, the choices in storage available, security, and the tools Azure provides to help customers migrate their workloads. This session will include a demonstration on what it takes to bring a workload to the cloud and run a job. 


DAC Pavilion – Bespoke Silicon - Tailor-Made for Maximum Performance 

Tuesday, July 13 | 2:00PM-3:00PM PT 

Prashant Varshney, Head of Product, Silicon, Microsoft Azure 

Bespoke (or tailored) silicon refers to chips and 3D-IC systems developed by a company for its exclusive use in its systems. Leading system companies such as Google, Tesla, Amazon, Apple and Microsoft have newly built or acquired IC design teams to design bespoke silicon to give themselves an advantage over their competitors using off-the-shelf chips. They are bringing their systems expertise into the 3D-IC chip design world and this is changing the dynamics of the semiconductor market in sometimes unexpected ways. This Pavilion roundtable gathers senior designers of Bespoke Silicon to discuss their motivations and experiences in this emerging market. 

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