Optimal MPI Process Placement for Azure HB Series VMs

Published Jun 18 2021 12:32 PM 1,927 Views
Microsoft

MPI Process Pinning for HB-series VMs

For MPI applications, optimal pinning of processes can lead to significant application performance improvements for under subscribed systems. Before AMD introduced the Chiplet design a few years back, to get the optimal performance the user just needed to decide if their application performed better running all on the same socket or equally balanced across the sockets. However, with the introduction of the Chiplet design, it became more complicated. The following is a link to a diagram that may help to better understand the chiplet design

In the chiplet design, AMD has essentially integrated a bunch of smaller CPUs together to provide a socket with 64 cores (8 - 16 smaller CPUs with 4-8 cores each). To maximize the performance from each core it is important to balance the amount of L3 cache and memory bandwidth per core.  We will discuss how to do this below for the following Azure HB VM types using IntelMPI and OpenMPI/HPC-X.

 

Azure HB VM:

This instance comes with 60 AMD Naples cores. Each socket contains 8 numa domain with 4 cores each. One 4 core numa domain is held back for the hypervisor leaving 15 numa domains for the user. When undersubscribing the VM to get the desired resources/core it is desirable to equally balance the L3 cache and memory bandwidth between cores. To do this the user will need to select either 15, 30, 45, or 60 cores per node.

 

Metrics Azure
HB60rs HB60rs HB60rs HB60rs
Cores (Physical) 15 30 45 60
RAM (GB) 224 224 224 224
Network (BW) (Gb/s) 100 100 100 100
Memory BW (GB/s) 250 250 250 250
RAM/Core (GB) 14.93 7.47 4.98 3.73
Network BW/Core (Gb/s) 6.67 3.33 2.22 1.67
Memory BW/Core (GB/s) 16.67 8.33 5.56 4.17

 

OpenMPI 4 / HPC-X:

Note: To print out the placement of the cores before the application is run add the flag --report-bindings

    --bind-to core --map-by ppr:1:numa (30 cores)

    --bind-to core --map-by ppr:2:numa (60 cores)

    --bind-to core --map-by ppr:3:numa (90 cores)

 

Intel MPI:

Note: To print out the placement of the cores before the application is run add the environment variable I_MPI_DEBUG=4

15 PPN:

-env I_MPI_PIN_PROCESSOR_LIST=$(echo "for (i=0;i<60;i+=4) for (j=0;j<1;j++) i+j" | bc | sed -z 's/\n/,/g;s/,$/\n/')

 

30 PPN:

-env I_MPI_PIN_PROCESSOR_LIST=$(echo "for (i=0;i<60;i+=4) for (j=0;j<2;j++) i+j" | bc | sed -z 's/\n/,/g;s/,$/\n/')

 

45 PPN:

-env I_MPI_PIN_PROCESSOR_LIST=$(echo "for (i=0;i<60;i+=4) for (j=0;j<3;j++) i+j" | bc | sed -z 's/\n/,/g;s/,$/\n/')

 

Azure HBv2 VM:

This instance comes with the 120 AMD Rome cores. Each socket contains 15 numa domain with 4 cores each. Two 4 core numa domain are held back for the hypervisor. When undersubscribing the HBv2 VM to get the desired resources/core it is desirable to equally balance the L3 cache and memory bandwidth between cores. To do this the user will need to select either 30, 60, 90, or 120 cores per node.

 

Metrics Azure
HB120rs_v2 HB120rs_v2 HB120rs_v2 HB120rs_v2
Cores (Physical) 30 60 90 120
RAM (GB) 448 448 448 448
Network (BW) (Gb/s) 200 200 200 200
Memory BW (GB/s) 345 345 345 345
RAM/Core (GB) 14.93 7.47 4.98 3.73
Network BW/Core (Gb/s) 6.67 3.33 2.22 1.67
Memory BW/Core (GB/s) 11.50 5.75 3.83 2.88

 

If  you want to undersubscribe your VM to get the optimal about of resources per core for you application then you can pin your processes to get the optimal placement for the 30, 60, or 90 cores. To do this you will need to add the following environment variables to your MPI jobs.

 

OpenMPI 4 / HPC-X:

Note: To print out the placement of the cores before the application is run add the flag --report-bindings

    --bind-to core --map-by ppr:1:numa (30 cores)

    --bind-to core --map-by ppr:2:numa (60 cores)

    --bind-to core --map-by ppr:3:numa (90 cores)

 

Intel MPI:

Note: To print out the placement of the cores before the application is run add the environment variable I_MPI_DEBUG=4

30 PPN:

-env I_MPI_PIN_PROCESSOR_LIST=$(echo "for (i=0;i<120;i+=4) for (j=0;j<1;j++) i+j" | bc | sed -z 's/\n/,/g;s/,$/\n/')

 

60 PPN:

-env I_MPI_PIN_PROCESSOR_LIST=$(echo "for (i=0;i<120;i+=4) for (j=0;j<2;j++) i+j" | bc | sed -z 's/\n/,/g;s/,$/\n/')

 

90 PPN:

-env I_MPI_PIN_PROCESSOR_LIST=$(echo "for (i=0;i<120;i+=4) for (j=0;j<3;j++) i+j" | bc | sed -z 's/\n/,/g;s/,$/\n/')

 

Azure HBv3 VM:

This instance comes with the 120 AMD Milan cores. Each socket contains 2 numa domain with 30 cores each. 2 cores from 4 chiplets are held back for the hypervisor. When undersubscribing the HBv3 VM to get the desired resources/core it is desirable to equally balance the L3 cache and memory bandwidth between cores. To do this the user will need to select either 16, 32, 64, 96, or 120 cores per node. To simplify the optimal process placement for our customers, we have provided additional HBv3 VM sizes (HB120-16rs_v3, HB120-32rs_v3, HB120-64rs_v3, HB120-96rs_v3) than the standard HB120rs_v3 size. Below you can see a table of the resources per core when using the various sizes.

 

Metrics Azure
HB120-16rs_v3 HB120-32rs_v3 HB120-64rs_v3 HB120-96rs_v3 HB120rs_v3
Cores (Physical) 16 32 64 96 120
RAM (GB) 448 448 448 448 448
Network (BW) (Gb/s) 200 200 200 200 200
Memory BW (GB/s) 345 345 345 345 345
RAM/Core (GB) 28.00 14.00 7.00 4.67 3.73
Network BW/Core (Gb/s) 12.50 6.25 3.13 2.08 1.67
Memory BW/Core (GB/s) 21.56 10.78 5.39 3.59 2.88

 

If you are using the HBv120rs_v3 size and you want to undersubscribe your VM to get the optimal about of resources per core for you application then you can pin your processes to the same cores used by the 16, 32, 64, or 96 core VM sizes. To do this you will need to add the following environment variables to your MPI jobs.

 

OpenMPI 4 / HPC-X:

Note: To print out the placement of the cores before the application is run add the flag --report-bindings

 

16 PPN:

--bind-to cpulist:ordered --cpu-set 0,8,16,24,30,38,46,54,60,68,76,84,90,98,106,114

 

32 PPN:

--bind-to cpulist:ordered 

--cpu-set 0,1,8,9,16,17,24,25,30,31,38,39,46,47,54,55,60,61,68,69,76,77,84,85,90,91,98,99,106,107,114,115

 

64 PPN:

--bind-to cpulist:ordered

--cpu-set 0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27,30,31,32,33,38,39,40,41,46,47,48,49,54,55,56,57,60,61,62,63,68,69,70,71,76,77,78,79,84,85,86,87,90,91,92,93,98,99,100,101,106,107,108,109,114,115,116,117

 

96 PPN:

--bind-to cpulist:ordered

--cpu-set 0,1,2,3,4,5,8,9,10,11,12,13,16,17,18,19,20,21,24,25,26,27,28,29,30,31,32,33,34,35,38,39,40,41,42,43,46,47,48,49,50,51,54,55,56,57,58,59,60,61,62,63,64,65,68,69,70,71,72,75,76,77,78,79,80,81,84,85,86,87,88,89,90,91,92,93,94,95,98,99,100,101,102,103,106,107,108,109,110,111,114,115,116,117,118,119

 

 

Intel MPI:

Note: To print out the placement of the cores before the application is run add the environment variable I_MPI_DEBUG=4

 

16 PPN:

-genv I_MPI_PIN_PROCESSOR_LIST= 0,8,16,24,30,38,46,54,60,68,76,84,90,98,106,114

 

32 PPN:

-genv I_MPI_PIN_PROCESSOR_LIST= 0,1,8,9,16,17,24,25,30,31,38,39,46,47,54,55,60,61,68,69,76,77,84,85,90,91,98,99,106,107,114,115

 

64 PPN:

-genv I_MPI_PIN_PROCESSOR_LIST=0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27,30,31,32,33,38,39,40,41,46,47,48,49,54,55,56,57,60,61,62,63,68,69,70,71,76,77,78,79,84,85,86,87,90,91,92,93,98,99,100,101,106,107,108,109,114,115,116,117

 

96 PPN:

-genv I_MPI_PIN_PROCESSOR_LIST=0,1,2,3,4,5,8,9,10,11,12,13,16,17,18,19,20,21,24,25,26,27,28,29,30,31,32,33,34,35,38,39,40,41,42,43,46,47,48,49,50,51,54,55,56,57,58,59,60,61,62,63,64,65,68,69,70,71,72,75,76,77,78,79,80,81,84,85,86,87,88,89,90,91,92,93,94,95,98,99,100,101,102,103,106,107,108,109,110,111,114,115,116,117,118,119

 

Pinning for Hybrid (MPI + OpenMP)

When running in hybrid mode on HBv3 you will need to exclude some cores to get the proper pinning. 

 

HB and HBv2

HB and HBv2 are laid out with chiplet represented as a numa domain. To get the optimal L3 cache usage you will only want to use 2, 3, or 4 threads per MPI rank. Below are the environment variables that you will need to set to get the optimal mpi placement. For HB you will want to only use 15 (2, 3, or 4 threads/rank) or 30 ( 2 threads/rank) mpi ranks. For HBv2 you will want to only use 30 (2, 3, or 4 threads/rank) or 60 ( 2 threads/rank) mpi ranks. 

 

OpenMPI 4 / HPC-X:

  • --bind-to core
  • --map-by ppr:<mpi ranks/numa>:numa:pe=<threads/mpi rank>

Example: If I wanted to run 30 MPI ranks on HBv2 and use 3 threads/rank (90 total cores) I would use the following options

  • -np 30
  • --bind-to core
  • --map-by ppr:1:numa:pe=3
  • OMP_NUM_THREADS=3

HBv3

  • Under investigation. If you know of a clean way to do this with OpenMPI that is equivalent to what Intel MPI does please share in the comments.

Intel MPI:

  • I_MPI_PIN=on
  • I_MPI_PIN_DOMAIN cache3
  • OMP_NUM_THREADS=[2,3, or 4]

Example: If I wanted to run 30 MPI ranks on HBv2 and use 2 threads/rank (60 total cores) I would use the following options

  • -np 30 (or some multiple of 30 * number of VMs)
  • I_MPI_PIN=on
  • I_MPI_PIN_DOMAIN cache3
  • OMP_NUM_THREADS=2

HBv3

The approach that we found that works with Intel MPI is to exclude the cores you do not want it to use and then by using the I_MPI_PIN_DOMAIN variable you can get it properly use the remaining cores. Below is the list of cores you would want to exclude if you were to run 96 (exclude 24), 64 (exclude 56), or 32 (exclude 88) cores/node.

 

Exclude Cores
Cores Core List
24 14,15,22,23,6,7,44,45,52,53,36,37,74,75,82,83,66,67,104,105,112,113,96,97
56 4,5,12,13,14,15,20,21,22,23,28,29,6,7,34,35,42,43,44,45,50,51,52,53,58,59,36,37,64,65,72,73,74,75,80,81,82,83,88,89,66,67,94,95,102,103,104,105,110,111,112,113,118,119,96,97
88 2,3,4,5,10,11,12,13,14,15,18,19,20,21,22,23,26,27,28,29,6,7,32,33,34,35,40,41,42,43,44,45,48,49,50,51,52,53,56,57,58,59,36,37,62,63,64,65,70,71,72,73,74,75,78,79,80,81,82,83,86,87,88,89,66,67,92,93,94,95,100,101,102,103,104,105,108,109,110,111,112,113,116,117,118,119,96,97

 

Recommendations for the following hybrid scenarios:

  • Note: If you use other combinations of ranks and threads you will not have optimal resource distribution for L3 cache and will span AMD chiplets which will reduce performance
MPI Ranks Threads/MPI rank Exclude Cores
16 6 24
32 3 24
48 2 24
16 4

56

32 2

56

16 2

88

 

To run in hybrid mode, you will want to set the following environment variables

  • I_MPI_PIN=on
  • I_MPI_PIN_DOMAIN <threads/mpi rank>:compact
  • I_MPI_PIN_PROCESSOR_EXCLUDE_LIST=<exclude core list>

Example: For 16 MPI ranks/node with 6 threads/rank ( 96 cores/node):       

    • I_MPI_PIN=on
    • I_MPI_PIN_DOMAIN 6:compact
    • I_MPI_PIN_PROCESSOR_EXCLUDE_LIST=14,15,22,23,6,7,44,45,52,53,36,37,74,75,82,83,66,67,104,105,112,113,96,97
%3CLINGO-SUB%20id%3D%22lingo-sub-2450663%22%20slang%3D%22en-US%22%3EOptimal%20MPI%20Process%20Placement%20for%20Azure%20HB%20Series%20VMs%3C%2FLINGO-SUB%3E%3CLINGO-BODY%20id%3D%22lingo-body-2450663%22%20slang%3D%22en-US%22%3E%3CP%3E%3CFONT%20size%3D%225%22%3E%3CSTRONG%3EMPI%20Process%20Pinning%20for%20HB-series%20VMs%3C%2FSTRONG%3E%3C%2FFONT%3E%3C%2FP%3E%0A%3CP%3EFor%20MPI%20applications%2C%20optimal%20pinning%20of%20processes%20can%20lead%20to%20significant%20application%20performance%20improvements%20for%20under%20subscribed%20systems.%20Before%20AMD%20introduced%20the%20Chiplet%20design%20a%20few%20years%20back%2C%20to%20get%20the%20optimal%20performance%20the%20user%20just%20needed%20to%20decide%20if%20their%20application%20performed%20better%20running%20all%20on%20the%20same%20socket%20or%20equally%20balanced%20across%20the%20sockets.%20However%2C%20with%20the%20introduction%20of%20the%20Chiplet%20design%2C%20it%20became%20more%20complicated.%20The%20following%20is%20a%20%3CA%20href%3D%22https%3A%2F%2Fpbs.twimg.com%2Fmedia%2FDqvNhO0U0AEpbvx.jpg%3Alarge%22%20target%3D%22_self%22%20rel%3D%22nofollow%20noopener%20noreferrer%22%3Elink%3C%2FA%3E%20to%20a%20diagram%20that%20may%20help%20to%20better%20understand%20the%20chiplet%20design%3C%2FP%3E%0A%3CP%3EIn%20the%20chiplet%20design%2C%20AMD%20has%20essentially%20integrated%20a%20bunch%20of%20smaller%20CPUs%20together%20to%20provide%20a%20socket%20with%2064%20cores%20(8%20-%2016%20smaller%20CPUs%20with%204-8%20cores%20each).%20To%20maximize%20the%20performance%20from%20each%20core%20it%20is%20important%20to%20balance%20the%20amount%20of%20L3%20cache%20and%20memory%20bandwidth%20per%20core.%26nbsp%3B%20We%20will%20discuss%20how%20to%20do%20this%20below%20for%20the%20following%20Azure%20HB%20VM%20types%20using%20IntelMPI%20and%20OpenMPI%2FHPC-X.%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSTRONG%3EAzure%20HB%20VM%3A%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CP%3EThis%20instance%20comes%20with%2060%20AMD%20Naples%20cores.%26nbsp%3BEach%20socket%20contains%208%20numa%20domain%20with%204%20cores%20each.%20One%204%20core%20numa%20domain%20is%20held%20back%20for%20the%20hypervisor%20leaving%2015%20numa%20domains%20for%20the%20user.%20When%20undersubscribing%20the%20VM%20to%20get%20the%20desired%20resources%2Fcore%20it%20is%20desirable%20to%20equally%20balance%20the%20L3%20cache%20and%20memory%20bandwidth%20between%20cores.%20To%20do%20this%20the%20user%20will%20need%20to%20select%20either%2015%2C%2030%2C%2045%2C%20or%2060%20cores%20per%20node.%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CTABLE%20style%3D%22width%3A%20840px%3B%22%20width%3D%22840%22%3E%0A%3CTBODY%3E%0A%3CTR%3E%0A%3CTD%20rowspan%3D%222%22%20width%3D%22300px%22%20height%3D%2260px%22%20class%3D%22lia-align-center%22%3EMetrics%3C%2FTD%3E%0A%3CTD%20colspan%3D%224%22%20width%3D%22539px%22%20height%3D%2230px%22%20class%3D%22lia-align-center%22%3EAzure%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22134px%22%20height%3D%2230px%22%20class%3D%22lia-align-center%22%3EHB60rs%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-center%22%3EHB60rs%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-center%22%3EHB60rs%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-center%22%3EHB60rs%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3ECores%20(Physical)%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E15%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E30%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E45%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E60%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3ERAM%20(GB)%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E224%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E224%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E224%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E224%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3ENetwork%20(BW)%20(Gb%2Fs)%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E100%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E100%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E100%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E100%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3EMemory%20BW%20(GB%2Fs)%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E250%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E250%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E250%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E250%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3ERAM%2FCore%20(GB)%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E14.93%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E7.47%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E4.98%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E3.73%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3ENetwork%20BW%2FCore%26nbsp%3B%3CSPAN%3E(Gb%2Fs)%3C%2FSPAN%3E%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E6.67%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E3.33%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E2.22%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E1.67%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3EMemory%20BW%2FCore%26nbsp%3B%3CSPAN%3E(GB%2Fs)%3C%2FSPAN%3E%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E16.67%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E8.33%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E5.56%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E4.17%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3C%2FTBODY%3E%0A%3C%2FTABLE%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSTRONG%3EOpenMPI%204%20%2F%20HPC-X%3A%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CP%3ENote%3A%20To%20print%20out%20the%20placement%20of%20the%20cores%20before%20the%20application%20is%20run%20add%20the%20flag%20--report-bindings%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%20%26nbsp%3B%20--bind-to%20core%20--map-by%20ppr%3A1%3Anuma%20(30%20cores)%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%20%26nbsp%3B%20--bind-to%20core%20--map-by%20ppr%3A2%3Anuma%20(60%20cores)%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%20%26nbsp%3B%20--bind-to%20core%20--map-by%20ppr%3A3%3Anuma%20(90%20cores)%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSTRONG%3EIntel%20MPI%3A%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CP%3ENote%3A%26nbsp%3BTo%20print%20out%20the%20placement%20of%20the%20cores%20before%20the%20application%20is%20run%20add%20the%20environment%20variable%26nbsp%3B%3CSPAN%20class%3D%22TextRun%20MacChromeBold%20%20BCX0%20SCXW171700561%22%20data-contrast%3D%22none%22%3E%3CSPAN%20class%3D%22NormalTextRun%20%20BCX0%20SCXW171700561%22%3EI_MPI_DEBUG%3D4%3C%2FSPAN%3E%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%3CSPAN%3E15%20PPN%3A%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%3CSPAN%3E-env%20I_MPI_PIN_PROCESSOR_LIST%3D%24(echo%20%22for%20(i%3D0%3Bi%26lt%3B60%3Bi%2B%3D4)%20for%20(j%3D0%3Bj%26lt%3B1%3Bj%2B%2B)%20i%2Bj%22%20%7C%20bc%20%7C%20sed%20-z%20's%2F%5Cn%2F%2C%2Fg%3Bs%2F%2C%24%2F%5Cn%2F')%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSPAN%3E30%20PPN%3A%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%3CSPAN%3E-env%20I_MPI_PIN_PROCESSOR_LIST%3D%24(echo%20%22for%20(i%3D0%3Bi%26lt%3B60%3Bi%2B%3D4)%20for%20(j%3D0%3Bj%26lt%3B2%3Bj%2B%2B)%20i%2Bj%22%20%7C%20bc%20%7C%20sed%20-z%20's%2F%5Cn%2F%2C%2Fg%3Bs%2F%2C%24%2F%5Cn%2F')%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSPAN%3E45%20PPN%3A%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%3CSPAN%3E-env%20I_MPI_PIN_PROCESSOR_LIST%3D%24(echo%20%22for%20(i%3D0%3Bi%26lt%3B60%3Bi%2B%3D4)%20for%20(j%3D0%3Bj%26lt%3B3%3Bj%2B%2B)%20i%2Bj%22%20%7C%20bc%20%7C%20sed%20-z%20's%2F%5Cn%2F%2C%2Fg%3Bs%2F%2C%24%2F%5Cn%2F')%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSTRONG%3EAzure%20HBv2%20VM%3A%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CP%3EThis%20instance%20comes%20with%20the%20120%20AMD%20Rome%20cores.%20Each%20socket%20contains%2015%20numa%20domain%20with%204%20cores%20each.%20Two%204%20core%20numa%20domain%20are%20held%20back%20for%20the%20hypervisor.%20When%20undersubscribing%20the%20HBv2%20VM%20to%20get%20the%20desired%20resources%2Fcore%20it%20is%20desirable%20to%20equally%20balance%20the%20L3%20cache%20and%20memory%20bandwidth%20between%20cores.%20To%20do%20this%20the%20user%20will%20need%20to%20select%20either%2030%2C%2060%2C%2090%2C%20or%20120%20cores%20per%20node.%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CTABLE%20style%3D%22width%3A%20840px%3B%22%20width%3D%22839px%22%3E%0A%3CTBODY%3E%0A%3CTR%3E%0A%3CTD%20rowspan%3D%222%22%20width%3D%22300px%22%20class%3D%22lia-align-center%22%3EMetrics%3C%2FTD%3E%0A%3CTD%20colspan%3D%224%22%20width%3D%22539px%22%20class%3D%22lia-align-center%22%3EAzure%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22134px%22%20class%3D%22lia-align-center%22%3EHB120rs_v2%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-center%22%3EHB120rs_v2%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-center%22%3EHB120rs_v2%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-center%22%3EHB120rs_v2%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3ECores%20(Physical)%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20class%3D%22lia-align-right%22%3E30%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E60%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E90%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E120%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3ERAM%20(GB)%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20class%3D%22lia-align-right%22%3E448%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E448%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E448%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E448%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3ENetwork%20(BW)%20(Gb%2Fs)%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20class%3D%22lia-align-right%22%3E200%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E200%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E200%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E200%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3EMemory%20BW%20(GB%2Fs)%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20class%3D%22lia-align-right%22%3E345%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E345%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E345%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E345%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3ERAM%2FCore%20(GB)%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20class%3D%22lia-align-right%22%3E14.93%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E7.47%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E4.98%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E3.73%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3ENetwork%20BW%2FCore%26nbsp%3B%3CSPAN%3E(Gb%2Fs)%3C%2FSPAN%3E%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20class%3D%22lia-align-right%22%3E6.67%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E3.33%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E2.22%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E1.67%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22300px%22%20height%3D%2230px%22%3EMemory%20BW%2FCore%26nbsp%3B%3CSPAN%3E(GB%2Fs)%3C%2FSPAN%3E%3C%2FTD%3E%0A%3CTD%20width%3D%22134px%22%20class%3D%22lia-align-right%22%3E11.50%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E5.75%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E3.83%3C%2FTD%3E%0A%3CTD%20width%3D%22135px%22%20class%3D%22lia-align-right%22%3E2.88%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3C%2FTBODY%3E%0A%3C%2FTABLE%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3EIf%26nbsp%3B%20you%20want%20to%20undersubscribe%20your%20VM%20to%20get%20the%20optimal%20about%20of%20resources%20per%20core%20for%20you%20application%20then%20you%20can%20pin%20your%20processes%20to%20get%20the%20optimal%20placement%20for%20the%2030%2C%2060%2C%20or%2090%20cores.%20To%20do%20this%20you%20will%20need%20to%20add%20the%20following%20environment%20variables%20to%20your%20MPI%20jobs.%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSTRONG%3EOpenMPI%204%20%2F%20HPC-X%3A%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CP%3ENote%3A%20To%20print%20out%20the%20placement%20of%20the%20cores%20before%20the%20application%20is%20run%20add%20the%20flag%20--report-bindings%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%20%26nbsp%3B%20--bind-to%20core%20--map-by%20ppr%3A1%3Anuma%20(30%20cores)%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%20%26nbsp%3B%20--bind-to%20core%20--map-by%20ppr%3A2%3Anuma%20(60%20cores)%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%20%26nbsp%3B%20--bind-to%20core%20--map-by%20ppr%3A3%3Anuma%20(90%20cores)%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSTRONG%3EIntel%20MPI%3A%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CP%3ENote%3A%26nbsp%3BTo%20print%20out%20the%20placement%20of%20the%20cores%20before%20the%20application%20is%20run%20add%20the%20environment%20variable%26nbsp%3B%3CSPAN%20class%3D%22TextRun%20MacChromeBold%20%20BCX0%20SCXW171700561%22%20data-contrast%3D%22none%22%3E%3CSPAN%20class%3D%22NormalTextRun%20%20BCX0%20SCXW171700561%22%3EI_MPI_DEBUG%3D4%3C%2FSPAN%3E%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%3CSPAN%3E30%20PPN%3A%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%3CSPAN%3E-env%20I_MPI_PIN_PROCESSOR_LIST%3D%24(echo%20%22for%20(i%3D0%3Bi%26lt%3B120%3Bi%2B%3D4)%20for%20(j%3D0%3Bj%26lt%3B1%3Bj%2B%2B)%20i%2Bj%22%20%7C%20bc%20%7C%20sed%20-z%20's%2F%5Cn%2F%2C%2Fg%3Bs%2F%2C%24%2F%5Cn%2F')%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSPAN%3E60%20PPN%3A%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%3CSPAN%3E-env%20I_MPI_PIN_PROCESSOR_LIST%3D%24(echo%20%22for%20(i%3D0%3Bi%26lt%3B120%3Bi%2B%3D4)%20for%20(j%3D0%3Bj%26lt%3B2%3Bj%2B%2B)%20i%2Bj%22%20%7C%20bc%20%7C%20sed%20-z%20's%2F%5Cn%2F%2C%2Fg%3Bs%2F%2C%24%2F%5Cn%2F')%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSPAN%3E90%20PPN%3A%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%3CSPAN%3E-env%20I_MPI_PIN_PROCESSOR_LIST%3D%24(echo%20%22for%20(i%3D0%3Bi%26lt%3B120%3Bi%2B%3D4)%20for%20(j%3D0%3Bj%26lt%3B3%3Bj%2B%2B)%20i%2Bj%22%20%7C%20bc%20%7C%20sed%20-z%20's%2F%5Cn%2F%2C%2Fg%3Bs%2F%2C%24%2F%5Cn%2F')%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSTRONG%3EAzure%20HBv3%20VM%3A%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CP%3EThis%20instance%20comes%20with%20the%20120%20AMD%20Milan%20cores.%20Each%20socket%20contains%202%20numa%20domain%20with%2030%20cores%20each.%202%20cores%20from%204%20chiplets%20are%20held%20back%20for%20the%20hypervisor.%20When%20undersubscribing%20the%20HBv3%20VM%20to%20get%20the%20desired%20resources%2Fcore%20it%20is%20desirable%20to%20equally%20balance%20the%20L3%20cache%20and%20memory%20bandwidth%20between%20cores.%20To%20do%20this%20the%20user%20will%20need%20to%20select%20either%2016%2C%2032%2C%2064%2C%2096%2C%20or%20120%20cores%20per%20node.%20To%20simplify%20the%20optimal%20process%20placement%20for%20our%20customers%2C%20we%20have%20provided%20additional%20HBv3%20VM%20sizes%20(HB120-16rs_v3%2C%20HB120-32rs_v3%2C%20HB120-64rs_v3%2C%20HB120-96rs_v3)%20than%20the%20standard%20HB120rs_v3%20size.%20Below%20you%20can%20see%20a%20table%20of%20the%20resources%20per%20core%20when%20using%20the%20various%20sizes.%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CTABLE%20style%3D%22height%3A%20354px%3B%20width%3A%20840px%3B%22%20width%3D%22839px%22%3E%0A%3CTBODY%3E%0A%3CTR%3E%0A%3CTD%20rowspan%3D%222%22%20width%3D%22254px%22%20height%3D%2296px%22%20class%3D%22lia-align-center%22%3EMetrics%3C%2FTD%3E%0A%3CTD%20colspan%3D%225%22%20width%3D%22585px%22%20height%3D%2233px%22%20class%3D%22lia-align-center%22%3EAzure%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2263px%22%20class%3D%22lia-align-center%22%3EHB120-16rs_v3%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2263px%22%20class%3D%22lia-align-center%22%3EHB120-32rs_v3%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2263px%22%20class%3D%22lia-align-center%22%3EHB120-64rs_v3%3C%2FTD%3E%0A%3CTD%20width%3D%22120px%22%20height%3D%2263px%22%20class%3D%22lia-align-center%22%3EHB120-96rs_v3%3C%2FTD%3E%0A%3CTD%20width%3D%22111px%22%20height%3D%2263px%22%20class%3D%22lia-align-center%22%3EHB120rs_v3%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22254px%22%20height%3D%2233px%22%3ECores%20(Physical)%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E16%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E32%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E64%3C%2FTD%3E%0A%3CTD%20width%3D%22120px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E96%3C%2FTD%3E%0A%3CTD%20width%3D%22111px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E120%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22254px%22%20height%3D%2233px%22%3ERAM%20(GB)%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E448%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E448%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E448%3C%2FTD%3E%0A%3CTD%20width%3D%22120px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E448%3C%2FTD%3E%0A%3CTD%20width%3D%22111px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E448%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22254px%22%20height%3D%2233px%22%3ENetwork%20(BW)%20(Gb%2Fs)%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E200%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E200%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E200%3C%2FTD%3E%0A%3CTD%20width%3D%22120px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E200%3C%2FTD%3E%0A%3CTD%20width%3D%22111px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E200%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22254px%22%20height%3D%2263px%22%3EMemory%20BW%20(GB%2Fs)%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2263px%22%20class%3D%22lia-align-right%22%3E345%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2263px%22%20class%3D%22lia-align-right%22%3E345%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2263px%22%20class%3D%22lia-align-right%22%3E345%3C%2FTD%3E%0A%3CTD%20width%3D%22120px%22%20height%3D%2263px%22%20class%3D%22lia-align-right%22%3E345%3C%2FTD%3E%0A%3CTD%20width%3D%22111px%22%20height%3D%2263px%22%20class%3D%22lia-align-right%22%3E345%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22254px%22%20height%3D%2233px%22%3ERAM%2FCore%20(GB)%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E28.00%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E14.00%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E7.00%3C%2FTD%3E%0A%3CTD%20width%3D%22120px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E4.67%3C%2FTD%3E%0A%3CTD%20width%3D%22111px%22%20height%3D%2233px%22%20class%3D%22lia-align-right%22%3E3.73%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22254px%22%20height%3D%2232px%22%3ENetwork%20BW%2FCore%26nbsp%3B%3CSPAN%3E(Gb%2Fs)%3C%2FSPAN%3E%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2232px%22%20class%3D%22lia-align-right%22%3E12.50%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2232px%22%20class%3D%22lia-align-right%22%3E6.25%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2232px%22%20class%3D%22lia-align-right%22%3E3.13%3C%2FTD%3E%0A%3CTD%20width%3D%22120px%22%20height%3D%2232px%22%20class%3D%22lia-align-right%22%3E2.08%3C%2FTD%3E%0A%3CTD%20width%3D%22111px%22%20height%3D%2232px%22%20class%3D%22lia-align-right%22%3E1.67%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%22254px%22%20height%3D%2230px%22%3EMemory%20BW%2FCore%26nbsp%3B%3CSPAN%3E(GB%2Fs)%3C%2FSPAN%3E%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E21.56%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E10.78%3C%2FTD%3E%0A%3CTD%20width%3D%22118px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E5.39%3C%2FTD%3E%0A%3CTD%20width%3D%22120px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E3.59%3C%2FTD%3E%0A%3CTD%20width%3D%22111px%22%20height%3D%2230px%22%20class%3D%22lia-align-right%22%3E2.88%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3C%2FTBODY%3E%0A%3C%2FTABLE%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3EIf%20you%20are%20using%20the%20HBv120rs_v3%20size%20and%20you%20want%20to%20undersubscribe%20your%20VM%20to%20get%20the%20optimal%20about%20of%20resources%20per%20core%20for%20you%20application%20then%20you%20can%20pin%20your%20processes%20to%20the%20same%20cores%20used%20by%20the%2016%2C%2032%2C%2064%2C%20or%2096%20core%20VM%20sizes.%20To%20do%20this%20you%20will%20need%20to%20add%20the%20following%20environment%20variables%20to%20your%20MPI%20jobs.%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSTRONG%3EOpenMPI%204%20%2F%20HPC-X%3A%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CP%3ENote%3A%20To%20print%20out%20the%20placement%20of%20the%20cores%20before%20the%20application%20is%20run%20add%20the%20flag%20--report-bindings%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E16%20PPN%3A%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E--bind-to%20cpulist%3Aordered%20--cpu-set%200%2C8%2C16%2C24%2C30%2C38%2C46%2C54%2C60%2C68%2C76%2C84%2C90%2C98%2C106%2C114%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E32%20PPN%3A%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E--bind-to%20cpulist%3Aordered%26nbsp%3B%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E--cpu-set%200%2C1%2C8%2C9%2C16%2C17%2C24%2C25%2C30%2C31%2C38%2C39%2C46%2C47%2C54%2C55%2C60%2C61%2C68%2C69%2C76%2C77%2C84%2C85%2C90%2C91%2C98%2C99%2C106%2C107%2C114%2C115%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E64%20PPN%3A%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E--bind-to%20cpulist%3Aordered%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E--cpu-set%200%2C1%2C2%2C3%2C8%2C9%2C10%2C11%2C16%2C17%2C18%2C19%2C24%2C25%2C26%2C27%2C30%2C31%2C32%2C33%2C38%2C39%2C40%2C41%2C46%2C47%2C48%2C49%2C54%2C55%2C56%2C57%2C60%2C61%2C62%2C63%2C68%2C69%2C70%2C71%2C76%2C77%2C78%2C79%2C84%2C85%2C86%2C87%2C90%2C91%2C92%2C93%2C98%2C99%2C100%2C101%2C106%2C107%2C108%2C109%2C114%2C115%2C116%2C117%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E96%20PPN%3A%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E--bind-to%20cpulist%3Aordered%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E%3CSPAN%3E--cpu-set%200%2C1%2C2%2C3%2C4%2C5%2C8%2C9%2C10%2C11%2C12%2C13%2C16%2C17%2C18%2C19%2C20%2C21%2C24%2C25%2C26%2C27%2C28%2C29%2C30%2C%3C%2FSPAN%3E%3CSPAN%3E31%2C32%2C33%2C%3C%2FSPAN%3E%3CSPAN%3E34%2C35%2C38%2C39%2C40%2C41%2C42%2C43%2C46%2C47%2C48%2C49%2C50%2C51%2C54%2C55%2C56%2C57%2C58%2C59%2C60%2C61%2C62%2C63%2C64%2C65%2C68%2C69%2C70%2C71%2C72%2C75%2C76%2C77%2C78%2C79%2C80%2C81%2C84%2C85%2C86%2C87%2C88%2C89%2C90%2C91%2C92%2C93%2C94%2C95%2C98%2C99%2C100%2C101%2C102%2C103%2C106%2C107%2C108%2C109%2C110%2C111%2C114%2C115%2C116%2C117%2C118%2C119%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSTRONG%3EIntel%20MPI%3A%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CP%3ENote%3A%26nbsp%3BTo%20print%20out%20the%20placement%20of%20the%20cores%20before%20the%20application%20is%20run%20add%20the%20environment%20variable%26nbsp%3B%3CSPAN%20class%3D%22TextRun%20MacChromeBold%20%20BCX0%20SCXW171700561%22%20data-contrast%3D%22none%22%3E%3CSPAN%20class%3D%22NormalTextRun%20%20BCX0%20SCXW171700561%22%3EI_MPI_DEBUG%3D4%3C%2FSPAN%3E%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E16%20PPN%3A%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E-genv%20I_MPI_PIN_PROCESSOR_LIST%3D%200%2C8%2C16%2C24%2C30%2C38%2C46%2C54%2C60%2C68%2C76%2C84%2C90%2C98%2C106%2C114%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E32%20PPN%3A%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E-genv%20I_MPI_PIN_PROCESSOR_LIST%3D%200%2C1%2C8%2C9%2C16%2C17%2C24%2C25%2C30%2C31%2C38%2C39%2C46%2C47%2C54%2C55%2C60%2C61%2C68%2C69%2C76%2C77%2C84%2C85%2C90%2C91%2C98%2C99%2C106%2C107%2C114%2C115%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E64%20PPN%3A%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E-genv%20I_MPI_PIN_PROCESSOR_LIST%3D0%2C1%2C2%2C3%2C8%2C9%2C10%2C11%2C16%2C17%2C18%2C19%2C24%2C25%2C26%2C27%2C30%2C31%2C32%2C33%2C38%2C39%2C40%2C41%2C46%2C47%2C48%2C49%2C54%2C55%2C56%2C57%2C60%2C61%2C62%2C63%2C68%2C69%2C70%2C71%2C76%2C77%2C78%2C79%2C84%2C85%2C86%2C87%2C90%2C91%2C92%2C93%2C98%2C99%2C100%2C101%2C106%2C107%2C108%2C109%2C114%2C115%2C116%2C117%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E96%20PPN%3A%3C%2FP%3E%0A%3CP%20class%3D%22xxxmsonormal%22%3E%3CSPAN%3E-genv%20I_MPI_PIN_PROCESSOR_LIST%3D0%2C1%2C2%2C3%2C4%2C5%2C8%2C9%2C10%2C11%2C12%2C13%2C16%2C17%2C18%2C19%2C20%2C21%2C24%2C25%2C26%2C27%2C28%2C29%2C30%2C%3C%2FSPAN%3E%3CSPAN%3E31%2C32%2C33%2C%3C%2FSPAN%3E%3CSPAN%3E34%2C35%2C38%2C39%2C40%2C41%2C42%2C43%2C46%2C47%2C48%2C49%2C50%2C51%2C54%2C55%2C56%2C57%2C58%2C59%2C60%2C61%2C62%2C63%2C64%2C65%2C68%2C69%2C70%2C71%2C72%2C75%2C76%2C77%2C78%2C79%2C80%2C81%2C84%2C85%2C86%2C87%2C88%2C89%2C90%2C91%2C92%2C93%2C94%2C95%2C98%2C99%2C100%2C101%2C102%2C103%2C106%2C107%2C108%2C109%2C110%2C111%2C114%2C115%2C116%2C117%2C118%2C119%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CFONT%20size%3D%225%22%3E%3CSTRONG%3EPinning%20for%20Hybrid%20(MPI%20%2B%20OpenMP)%3C%2FSTRONG%3E%3C%2FFONT%3E%3C%2FP%3E%0A%3CP%3EWhen%20running%20in%20hybrid%20mode%20on%20HBv3%20you%20will%20need%20to%20exclude%20some%20cores%20to%20get%20the%20proper%20pinning.%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSTRONG%3EHB%20and%20HBv2%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CP%3EHB%20and%20HBv2%20are%20laid%20out%20with%20chiplet%20represented%20as%20a%20numa%20domain.%20To%20get%20the%20optimal%20L3%20cache%20usage%20you%20will%20only%20want%20to%20use%202%2C%203%2C%20or%204%20threads%20per%20MPI%20rank.%20Below%20are%20the%20environment%20variables%20that%20you%20will%20need%20to%20set%20to%20get%20the%20optimal%20mpi%20placement.%20For%20HB%20you%20will%20want%20to%20only%20use%2015%20(2%2C%203%2C%20or%204%20threads%2Frank)%20or%2030%20(%202%20threads%2Frank)%20mpi%20ranks.%20For%20HBv2%20you%20will%20want%20to%20only%20use%2030%20(2%2C%203%2C%20or%204%20threads%2Frank)%20or%2060%20(%202%20threads%2Frank)%20mpi%20ranks.%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3E%3CSTRONG%3EOpenMPI%204%20%2F%20HPC-X%3A%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CUL%3E%0A%3CLI%3E--bind-to%20core%3C%2FLI%3E%0A%3CLI%3E--map-by%20ppr%3A%3CMPI%20ranks%3D%22%22%3E%3Anuma%3Ape%3D%3CTHREADS%3E%3C%2FTHREADS%3E%3C%2FMPI%3E%3C%2FLI%3E%0A%3C%2FUL%3E%0A%3CP%3EExample%3A%20If%20I%20wanted%20to%20run%2030%20MPI%20ranks%20on%20HBv2%20and%20use%203%20threads%2Frank%20(90%20total%20cores)%20I%20would%20use%20the%20following%20options%3C%2FP%3E%0A%3CUL%3E%0A%3CLI%3E-np%2030%3C%2FLI%3E%0A%3CLI%3E--bind-to%20core%3C%2FLI%3E%0A%3CLI%3E--map-by%20ppr%3A1%3Anuma%3Ape%3D3%3C%2FLI%3E%0A%3CLI%3EOMP_NUM_THREADS%3D3%3C%2FLI%3E%0A%3C%2FUL%3E%0A%3CP%3E%3CSTRONG%3EHBv3%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CUL%3E%0A%3CLI%3EUnder%20investigation.%20If%20you%20know%20of%20a%20clean%20way%20to%20do%20this%20with%20OpenMPI%20that%20is%20equivalent%20to%20what%20Intel%20MPI%20does%20please%20share%20in%20the%20comments.%3C%2FLI%3E%0A%3C%2FUL%3E%0A%3CP%3E%3CSTRONG%3EIntel%20MPI%3A%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CUL%3E%0A%3CLI%3EI_MPI_PIN%3Don%3C%2FLI%3E%0A%3CLI%3EI_MPI_PIN_DOMAIN%20cache3%3C%2FLI%3E%0A%3CLI%3EOMP_NUM_THREADS%3D%5B2%2C3%2C%20or%204%5D%3C%2FLI%3E%0A%3C%2FUL%3E%0A%3CP%3EExample%3A%20If%20I%20wanted%20to%20run%2030%20MPI%20ranks%20on%20HBv2%20and%20use%202%20threads%2Frank%20(60%20total%20cores)%20I%20would%20use%20the%20following%20options%3C%2FP%3E%0A%3CUL%3E%0A%3CLI%3E-np%2030%20(or%20some%20multiple%20of%2030%20*%20number%20of%20VMs)%3C%2FLI%3E%0A%3CLI%3EI_MPI_PIN%3Don%3C%2FLI%3E%0A%3CLI%3EI_MPI_PIN_DOMAIN%20cache3%3C%2FLI%3E%0A%3CLI%3EOMP_NUM_THREADS%3D2%3C%2FLI%3E%0A%3C%2FUL%3E%0A%3CP%3E%3CSTRONG%3EHBv3%3C%2FSTRONG%3E%3C%2FP%3E%0A%3CP%3EThe%20approach%20that%20we%20found%20that%20works%20with%20Intel%20MPI%20is%20to%20exclude%20the%20cores%20you%20do%20not%20want%20it%20to%20use%20and%20then%20by%20using%20the%20I_MPI_PIN_DOMAIN%20variable%20you%20can%20get%20it%20properly%20use%20the%20remaining%20cores.%20Below%20is%20the%20list%20of%20cores%20you%20would%20want%20to%20exclude%20if%20you%20were%20to%20run%2096%20(exclude%2024)%2C%2064%20(exclude%2056)%2C%20or%2032%20(exclude%2088)%20cores%2Fnode.%3C%2FP%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CTABLE%20style%3D%22border-collapse%3A%20collapse%3B%20width%3A%20106pt%3B%22%20border%3D%220%22%20width%3D%22142%22%20cellspacing%3D%220%22%20cellpadding%3D%220%22%3E%0A%3CTBODY%3E%0A%3CTR%20style%3D%22height%3A%2015.0pt%3B%22%3E%0A%3CTD%20colspan%3D%222%22%20width%3D%22142%22%20height%3D%2220%22%20class%3D%22xl65%22%20style%3D%22height%3A%2015.0pt%3B%20width%3A%20106pt%3B%22%3EExclude%20Cores%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%20style%3D%22height%3A%2015.0pt%3B%22%3E%0A%3CTD%20height%3D%2220%22%20style%3D%22height%3A%2015.0pt%3B%22%3ECores%3C%2FTD%3E%0A%3CTD%3ECore%20List%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%20style%3D%22height%3A%2015.0pt%3B%22%3E%0A%3CTD%20height%3D%2220%22%20style%3D%22height%3A%2015.0pt%3B%22%3E24%3C%2FTD%3E%0A%3CTD%3E14%2C15%2C22%2C23%2C6%2C7%2C44%2C45%2C52%2C53%2C36%2C37%2C74%2C75%2C82%2C83%2C66%2C67%2C104%2C105%2C112%2C113%2C96%2C97%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%20style%3D%22height%3A%2015.0pt%3B%22%3E%0A%3CTD%20height%3D%2220%22%20style%3D%22height%3A%2015.0pt%3B%22%3E56%3C%2FTD%3E%0A%3CTD%3E4%2C5%2C12%2C13%2C14%2C15%2C20%2C21%2C22%2C23%2C28%2C29%2C6%2C7%2C34%2C35%2C42%2C43%2C44%2C45%2C50%2C51%2C52%2C53%2C58%2C59%2C36%2C37%2C64%2C65%2C72%2C73%2C74%2C75%2C80%2C81%2C82%2C83%2C88%2C89%2C66%2C67%2C94%2C95%2C102%2C103%2C104%2C105%2C110%2C111%2C112%2C113%2C118%2C119%2C96%2C97%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%20style%3D%22height%3A%2015.0pt%3B%22%3E%0A%3CTD%20height%3D%2220%22%20style%3D%22height%3A%2015.0pt%3B%22%3E88%3C%2FTD%3E%0A%3CTD%3E2%2C3%2C4%2C5%2C10%2C11%2C12%2C13%2C14%2C15%2C18%2C19%2C20%2C21%2C22%2C23%2C26%2C27%2C28%2C29%2C6%2C7%2C32%2C33%2C34%2C35%2C40%2C41%2C42%2C43%2C44%2C45%2C48%2C49%2C50%2C51%2C52%2C53%2C56%2C57%2C58%2C59%2C36%2C37%2C62%2C63%2C64%2C65%2C70%2C71%2C72%2C73%2C74%2C75%2C78%2C79%2C80%2C81%2C82%2C83%2C86%2C87%2C88%2C89%2C66%2C67%2C92%2C93%2C94%2C95%2C100%2C101%2C102%2C103%2C104%2C105%2C108%2C109%2C110%2C111%2C112%2C113%2C116%2C117%2C118%2C119%2C96%2C97%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3C%2FTBODY%3E%0A%3C%2FTABLE%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3ERecommendations%20for%20the%20following%20hybrid%20scenarios%3A%3C%2FP%3E%0A%3CUL%3E%0A%3CLI%3ENote%3A%20If%20you%20use%20other%20combinations%20of%20ranks%20and%20threads%20you%20will%20not%20have%20optimal%20resource%20distribution%20for%20L3%20cache%20and%20will%20span%20AMD%20chiplets%20which%20will%20reduce%20performance%3C%2FLI%3E%0A%3C%2FUL%3E%0A%3CTABLE%20border%3D%221%22%20width%3D%22100%25%22%3E%0A%3CTBODY%3E%0A%3CTR%3E%0A%3CTD%20width%3D%2233.333333333333336%25%22%3EMPI%20Ranks%3C%2FTD%3E%0A%3CTD%20width%3D%2233.333333333333336%25%22%3EThreads%2FMPI%20rank%3C%2FTD%3E%0A%3CTD%20width%3D%2233.333333333333336%25%22%3EExclude%20Cores%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%2233.333333333333336%25%22%3E16%3C%2FTD%3E%0A%3CTD%20width%3D%2233.333333333333336%25%22%3E6%3C%2FTD%3E%0A%3CTD%20width%3D%2233.333333333333336%25%22%3E24%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%20width%3D%2233.333333333333336%25%22%3E32%3C%2FTD%3E%0A%3CTD%20width%3D%2233.333333333333336%25%22%3E3%3C%2FTD%3E%0A%3CTD%20width%3D%2233.333333333333336%25%22%3E24%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%3E48%3C%2FTD%3E%0A%3CTD%3E2%3C%2FTD%3E%0A%3CTD%3E24%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%3E16%3C%2FTD%3E%0A%3CTD%3E4%3C%2FTD%3E%0A%3CTD%3E%3CP%3E56%3C%2FP%3E%0A%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%3E32%3C%2FTD%3E%0A%3CTD%3E2%3C%2FTD%3E%0A%3CTD%3E%3CP%3E56%3C%2FP%3E%0A%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3CTR%3E%0A%3CTD%3E16%3C%2FTD%3E%0A%3CTD%3E2%3C%2FTD%3E%0A%3CTD%3E%3CP%3E88%3C%2FP%3E%0A%3C%2FTD%3E%0A%3C%2FTR%3E%0A%3C%2FTBODY%3E%0A%3C%2FTABLE%3E%0A%3CP%3E%26nbsp%3B%3C%2FP%3E%0A%3CP%3ETo%20run%20in%20hybrid%20mode%2C%20you%20will%20want%20to%20set%20the%20following%20environment%20variables%3C%2FP%3E%0A%3CUL%3E%0A%3CLI%3EI_MPI_PIN%3Don%3C%2FLI%3E%0A%3CLI%3EI_MPI_PIN_DOMAIN%20%3CTHREADS%3E%3Acompact%3C%2FTHREADS%3E%3C%2FLI%3E%0A%3CLI%3EI_MPI_PIN_PROCESSOR_EXCLUDE_LIST%3D%3CEXCLUDE%20core%3D%22%22%20list%3D%22%22%3E%3C%2FEXCLUDE%3E%3C%2FLI%3E%0A%3C%2FUL%3E%0A%3CP%3EExample%3A%20For%2016%20MPI%20ranks%2Fnode%20with%206%20threads%2Frank%20(%2096%20cores%2Fnode)%3A%26nbsp%3B%26nbsp%3B%26nbsp%3B%26nbsp%3B%26nbsp%3B%26nbsp%3B%26nbsp%3B%3C%2FP%3E%0A%3CUL%3E%0A%3CUL%3E%0A%3CLI%3EI_MPI_PIN%3Don%3C%2FLI%3E%0A%3CLI%3EI_MPI_PIN_DOMAIN%206%3Acompact%3C%2FLI%3E%0A%3CLI%3EI_MPI_PIN_PROCESSOR_EXCLUDE_LIST%3D14%2C15%2C22%2C23%2C6%2C7%2C44%2C45%2C52%2C53%2C36%2C37%2C74%2C75%2C82%2C83%2C66%2C67%2C104%2C105%2C112%2C113%2C96%2C97%3C%2FLI%3E%0A%3C%2FUL%3E%0A%3C%2FUL%3E%3C%2FLINGO-BODY%3E%3CLINGO-TEASER%20id%3D%22lingo-teaser-2450663%22%20slang%3D%22en-US%22%3E%3CP%3E%3CSPAN%3EFor%20MPI%20applications%2C%20optimal%20pinning%20of%20processes%20can%20lead%20to%20significant%20application%20performance%20improvements%20for%20under%20subscribed%20systems.%3C%2FSPAN%3E%3C%2FP%3E%3C%2FLINGO-TEASER%3E%3CLINGO-LABS%20id%3D%22lingo-labs-2450663%22%20slang%3D%22en-US%22%3E%3CLINGO-LABEL%3EAzure%3C%2FLINGO-LABEL%3E%3CLINGO-LABEL%3EHPC%3C%2FLINGO-LABEL%3E%3CLINGO-LABEL%3EMPI%3C%2FLINGO-LABEL%3E%3C%2FLINGO-LABS%3E
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‎Jul 08 2021 02:33 PM
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