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Using FileX on internal microcontroller flash
Any support or examples on using FileX on internal microcontroller flash? I know there are complications in writing while executing from flash but some processors have hardware provisions to support this or other work arounds like running from SRAM while programming. I am envisioning this for modest amounts of mainly configuration data or static web pages.suppress incompatible pointer types in Azure RTOS demo program
I am bringing up Azure RTOS on a new ARM M4 platform. Most everything is built and running. I patterned the port closely after the Microchip ATSAME54-XPRO ARM M4 getting stated platform. I removed the Azure IoT main.c and replaced it with the simple demo test program as described on Chapter 6 - Demonstration System for Azure RTOS ThreadX | Microsoft Docs When I compile I am getting this warning/error that do not know how to suppress: Can some one help? ty_module/inc -IC:/ti/workspace_v10_test/getting-started/core/lib/netxduo/addons/azure_iot/azure_iot_security_module/iot-security-module-core/inc -I../lib/ti_start/config -I../lib/ti_start/src -Ic:/ti/simplelink_msp432e4_sdk_4_20_00_12/source/third_party/CMSIS/Include -IC:/ti/workspace_v10_test/getting-started/core/src/. -IC:/ti/workspace_v10_test/getting-started/core/src/azure_iot_mqtt -IC:/ti/workspace_v10_test/getting-started/core/src/azure_iot_nx -IC:/ti/workspace_v10_test/getting-started/core/lib/jsmn/src -I../lib/netx_driver/src -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 --specs=nano.specs -ffunction-sections -fdata-sections -fno-strict-aliasing -fno-builtin -fshort-enums -Wall -Wextra -Wuninitialized -Wshadow -Wdouble-promotion -Werror -Wno-unused-parameter -Wno-old-style-declaration -O0 -g3 -std=gnu99 -MD -MT app/CMakeFiles/msp432e_azure_iot.dir/maindemo.c.obj -MF app\CMakeFiles\msp432e_azure_iot.dir\maindemo.c.obj.d -o app/CMakeFiles/msp432e_azure_iot.dir/maindemo.c.obj -c ../app/maindemo.c ../app/maindemo.c: In function 'tx_application_define': ../app/maindemo.c:79:36: error: passing argument 2 of '_txe_byte_allocate' from incompatible pointer type [-Werror=incompatible-pointer-types] 79 | tx_byte_allocate(&byte_pool_0, &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); | ^~~~~~~~ | | | CHAR ** {aka char **} In file included from ../app/maindemo.c:10: C:/ti/workspace_v10_test/getting-started/core/lib/threadx/common/inc/tx_api.h:1396:63: note: expected 'void **' but argument is of type 'CHAR **' {aka 'char **'} 1396 | UINT _txe_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ../app/maindemo.c:87:36: error: passing argument 2 of '_txe_byte_allocate' from incompatible pointer type [-Werror=incompatible-pointer-types] 87 | tx_byte_allocate(&byte_pool_0, &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); | ^~~~~~~~ | | | CHAR ** {aka char **} In file included from ../app/maindemo.c:10: C:/ti/workspace_v10_test/getting-started/core/lib/threadx/common/inc/tx_api.h:1396:63: note: expected 'void **' but argument is of type 'CHAR **' {aka 'char **'} 1396 | UINT _txe_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ../app/maindemo.c:97:36: error: passing argument 2 of '_txe_byte_allocate' from incompatible pointer type [-Werror=incompatible-pointer-types] 97 | tx_byte_allocate(&byte_pool_0, &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); | ^~~~~~~~ | | | CHAR ** {aka char **} In file included from ../app/maindemo.c:10: C:/ti/workspace_v10_test/getting-started/core/lib/threadx/common/inc/tx_api.h:1396:63: note: expected 'void **' but argument is of type 'CHAR **' {aka 'char **'} 1396 | UINT _txe_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ../app/maindemo.c:103:36: error: passing argument 2 of '_txe_byte_allocate' from incompatible pointer type [-Werror=incompatible-pointer-types] 103 | tx_byte_allocate(&byte_pool_0, &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); | ^~~~~~~~ | | | CHAR ** {aka char **} In file included from ../app/maindemo.c:10:
LevelX with SDCard
I am looking at LevelX to use with an SD Card. I see that LevelX uses the 'spare' byes on each page. It appears that the extra, say, 16 bytes on a 512 byte nominal page means there is actually 528 bytes per page. This accords with my experience with small NAND Serial Data Flash chips where I have direct access to 528 bytes per page. I'm new to using SD Cards so I'm not too familiar with the spec. Are the extra bytes available to read/write? The SD Card I'm using reports 512 bytes per page. I cannot see or find any way to access the extra bytes. I'm using the i.MXRT 1064 with NXP's SDK (fsl_sd.c, fsl_sdmmc.c, etc.) Or, is LevelX not advisable for SD Cards? I understand that at least some SD Cards have wear leveling built in, but I didn't think it was universal. Am I wrong in this assumption?
Custom HID Device on USBx stack on STM32
Hello, Can someone, please, tell me where is a proper place to set a report size for an IN endpoint? USBD_HID_EPIN_FS_MPS configured to any value above 9 causes suspension of the interface. No matter what is written in the HID descriptor (and OUT reports are handled well), this value higher than 9 cases suspension. Whereas I need to send a reports with 55 bytes of data.
STM32 NetX Duo LwM2M Firmware Update
I have a project with STM32 MCU and BG95 LTE module. I use NetX Duo with LwM2M protocol. I am trying to implement FOTA for STM32 with LwM2M protocol. I haven't find resources for that. Is there any example for that? How can I implement that function? (Any suggestions)
NetXDuo mDNS domain set issue
Hello, My issue is related to:- MCU: STM32H733 Middleware: Azure RTOS Middleware Component: NetxDuo (6.2.0) Addon: mDNS I am using Azure RTOS with NetxDuo, I implemented a secure https server in my device and implemented mDNS which was working very well for me till I required to change domain. I want to add a sub-domain like (myhostname.mysubdomain.local). In documentation it is stated that by default the domain is .local but can be changed using nx_mdns_domain_name_set API Now, I have implemented this API in my code like this: ``` status = nx_mdns_create(&mdns_instance, &ip_instance, &netxduo_packet_pool, MDNS_PRIORITY, mdns_thread_stack, sizeof(mdns_thread_stack), (UCHAR *)hostname, (VOID *)local_service_cache, sizeof(local_service_cache), (VOID *)peer_service_cache, sizeof(peer_service_cache), NX_NULL); if (status != NX_SUCCESS) { Error_Handler(); } status = nx_mdns_domain_name_set(&mdns_instance, "home"); status = nx_mdns_enable(&mdns_instance, PRIMARY_INTERFACE); ``` It returns success and according to the document I must be able to ping hostname.home but thats not the case not matter what I done it will be always accessible through hostname.local I checked the domain name buffer inside mdns_instance, its updated to home but even then changed domain is not accessible. Goal: To be able to add subdomain Bigger Picture: I want to use wild card while generating certificate and keys in alt name and CN so that same certificate can be used in many devices thats why I need subdomain as it allows wild card in *.example.local not in *.local
Issue in configuring USBX in non-secure world on Trustzone board STM32U585
I am facing issue in running the thread USBX application in non-secure world on STM32U585. Below is the problem description and solution I tried. Problem Description : I am trying to run USBX application in non-secure world and SAES-GCM crypto application in secure world. The crypto application is working fine meaning able to encrypt and decrypt the data. But as it switches to non-secure world, after the Initialization, application stuck in I2C error occurred API, when trying to initialize CAD (USPD_CAD_Init “API name”). As this API is library API, I am not able to further debug it. Solution tried : We set SystemClock to 16MHZ with PLL source = HSI and systemclock is configured only from secure world Do we need to configure SystemClock in both the world or it is done once only? If building standalone USBX application after disabling the trustzone, it is working fine. May be I am setting some of the configuration wrong, so can anyone guide us on this. Below is the Clock Configuration I am configuring in secure world(assuming it will help to configure clock of both world) /***********************Clock Configuration Begins******************************************** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_CRSInitTypeDef RCC_CRSInitStruct = {0}; HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) /* MSI Oscillator enabled at reset (4Mhz), activate PLL with MSI as source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI |RCC_OSCILLATORTYPE_SHSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; // RCC_OscInitStruct.MSIState = RCC_MSI_ON; //RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; // RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_4; RCC_OscInitStruct.SHSIState = RCC_SHSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; // RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1; RCC_OscInitStruct.PLL.PLLM = 1; RCC_OscInitStruct.PLL.PLLN = 10;// 80 from crypto RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 2; RCC_OscInitStruct.PLL.PLLR = 1; //2 for crypto RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1; //for crypto RCC_PLLVCIRANGE_0 RCC_OscInitStruct.PLL.PLLFRACN= 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { /* Initialization Error */ while(1); } /* Select PLL as system clock source and configure bus clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | \ RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { Error_Handler(); /* Initialization Error */ } __HAL_RCC_CRS_CLK_ENABLE(); /** Configures CRS */ RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB; RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING; RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000); RCC_CRSInitStruct.ErrorLimitValue = 34; RCC_CRSInitStruct.HSI48CalibrationValue = 32; HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); /********************************Clock Configuration Ends*****************************************************/
Scheduling overhead
Hello I was asked to quantify how many CPU cycles are required for scheduling. I'm going to do an initial development for a series of devices. Could someone guide me to a place where I can find the number of CPU cycles to do the following: Preempt low priority thread and schedule high priority thread. Schedule from thread to thread on same priority. E.g. first thread blocked on a semaphore. Schedule from inactivated (e.g. blocking on a semaphore) high priority thread to low priority pending thread. Number of cycles from interrupt becoming active until first instruction of the user interrupt handler. Schedule from end of interrupt back to the thread preempted by this interrupt. Schedule from end of interrupt to a task higher than the thread that the interrupt has preempted. For how many CPU cycles get interrupts disabled while scheduling? I expect the applications will run under the following: Cortex-M0+/M4/M7 depending on the enabled features. A typical configuration for an application with 16-64 tasks and 8 priority levels How much adds an FPU? How much adds an MMU/MPU? Thanks very much
