At the Open Compute Project Global Summit, we introduced six open security innovations spanning hardware-protected key management, platform resilience, system-wide attestation, scalable bare-metal management, recovery, and silicon hardening:
- Tessera Integrated HSM, an open-source silicon HSM designed to scale with modern workloads while protecting keys and credentials to the highest industry standards.
- Platform Integrated TPM, a system TPM designed to improve security and recoverability while maintaining always-available host system measurements
. - Composite Entity Attestation Token (EAT), a whole-system attestation solution that aggregates attestation evidence from components across the system.
- Hierarchical Hardware Management, an architecture for modular hardware management that separates control environments for system and control plane.
- Network Recovery, an extension of OCP Streaming Boot that enables immutable BMC recovery through a unified boot and recovery path.
- Caliptra 2.2, scheduled for release in December, adds USB Streaming Boot and a smaller, fully masked Adams Bridge post-quantum cryptography accelerator.
Together, these technologies advance hardware security and resiliency. Each section below explains one innovation, the challenge it addresses, and how it contributes to the broader design.
Tessera Integrated HSM is an open-source silicon HSM initiative developed by Microsoft with Marvell®, Oracle, and the Open Compute Project. It represents an evolution of the Azure Integrated HSM workload-attached architecture, opening its specifications, protocols, drivers, software, firmware, and reproducible build environments, with a path toward fully open-source silicon. Building on the collaborative model established with Caliptra, Tessera Integrated HSM extends this approach to hardware key protection, enabling greater transparency and interoperability across the ecosystem.
Tessera Integrated HSM is designed for a security landscape being reshaped by AI and quantum computing. As AI increases the speed and scale of cyberattacks, protecting cryptographic keys, credentials, and other high-value digital assets has never been more critical. At the same time, advances in quantum computing are increasing the urgency of the transition to post-quantum cryptography.
Azure Integrated HSM was designed for this evolving landscape, continuously protecting keys in hardware while expanding access to quantum-resilient cryptography. Tessera builds on the lessons learned from deploying this architecture at Azure scale and extends them through open industry collaboration.
Tessera adopts the workload-attached Integrated HSM model to address fundamental limitations of centralized HSM architectures. Network latency, availability dependencies, operational complexity, and limited interoperability can lead organizations to generate, export, or cache keys outside the HSM, weakening the protections the HSM is intended to provide.
By bringing hardware key protection closer to the workload, Tessera enables keys to remain protected while improving interoperability, crypto-agility, and the transition to post-quantum cryptography. Its fully open-source architecture combines these benefits with the performance required for demanding workloads, supporting thousands of post-quantum key operations per second.
At the Open Compute Project Global Summit, Microsoft and Marvell® demonstrate Tessera interoperability through an Integrated HSM ring spanning Azure Integrated HSM hardware and Marvell® LiquidSecurity 2 HSM hardware, with keys remaining protected within the HSM security boundaries.
Tessera also extends to systems without dedicated Integrated HSM hardware. The Open Compute Project community has developed a model that runs the same Tessera firmware in hardware-isolated confidential computing environments, initially demonstrated with AMD SEV-SNP and community work already underway to extend the model to other confidential computing architectures.
These deployment models provide a common architecture and programming model, across different assurance levels. Confidential computing extends hardware-isolated key protection to systems without dedicated HSM hardware, while Tessera Integrated HSM provides dedicated, tamper-resistant key protection for high assurance environments.
Figure 2 Tessera Sealing Service for Integrated HSM
The open-source Tessera repository includes the firmware, drivers, software, and sealing services needed to operate enclaves and Tessera compliant hardware. The community has already begun the development of fully open-source silicon for compliant Tessera devices. Together, the open-source confidential computing Tessera enclave, open-source firmware and services, enables the broader adoption of open, scalable, interoperable hardware-backed key protection.
In 2022, Microsoft introduced Hydra, a security-centered Baseboard Management Controller (BMC) architecture built around hardware isolation. Hydra integrated the Platform Root of Trust (PRoT) into the BMC chip, consolidating capabilities traditionally provided by discrete platform security components into an integrated root of trust and companion security processor. This design enabled stronger runtime control of the BMC while isolating the security subsystem from the BMC’s management processors and interconnects.
At the Open Compute Project Global Summit, we demonstrated the next step in this evolution: moving the server’s traditional discrete host TPM functionality into the BMC root of trust security subsystem co-processor. The host CPU continues to provide and retrieve measurements through the standard TPM interface. However, unlike a traditional discrete TPM, the integrated design also makes measurements independently available through the BMC. The source code for the security coprocessor integrated TPM, is available in GitHub.
This out-of-band path enables both TPM measurements and system attestation throughout the server lifecycle, even when the host operating system is unavailable, has not fully booted, or lacks a TPM software stack. Platform integrity can therefore be evaluated independently of the host software environment.
Figure 3 Platform Integrated TPM
This capability is particularly relevant to modern virtualization architectures that do not have traditional host management partitions. Integrating host TPM functionality into the BMC root of trust security subsystem maintains an independent, always-available path to host measurements while preserving hardware isolation between security and management functions. In addition, the architecture supports the secure “Kirkland” transport binding we announced in 2022, while simplifying the attestation and recovery of the TPM itself.
As major BMC silicon manufacturers adopt Caliptra as their preferred root of trust security subsystem, the coprocessor integrated TPM architecture benefits from Caliptra's hardware key protection and dedicated DICE Protection Engine (DPE) contexts.
Composite Entity Attestation Token (EAT)
Modern platforms contain many independently attestable components such as, CPUs, GPUs, solid-state drives, network adapters, and other devices. Establishing trust requires a verifier to understand the system’s composition, identify each component, and retrieve its attestation evidence independently. As systems become more disaggregated, this process grows more complex and can require repeated interactions between the remote attestation service and the platform.
Composite Entity Attestation Token (EAT) provides a more scalable approach. Instead of requiring a verifier to discover and attest each component separately, the platform returns one signed attestation that cryptographically binds platform measurements to evidence from its constituent devices. The BMC collects fresh evidence from each component, and its integrated root-of-trust security subsystem binds those claims with the BMC measurements into a single platform attestation claim.
Figure 4 Composite EAT
The approach preserves each device’s native attestation evidence. CPUs, GPUs, storage devices, and other components continue using their existing mechanisms and evidence formats while that evidence is bound to the platform attestation. It also minimizes trust in collection and transport infrastructure: a collector can assemble the composite evidence without being trusted for the integrity of the underlying component claims.
This platform evidence bundle provides a foundation for simpler, interoperable attestation across increasingly disaggregated systems. The approach has been contributed to the Open Compute Project, with reference implementations on Azure GitHub and integrated into major BMC SDKs (Aspeed RoT, Aspeed BMC, Nuvoton RoT, Nuvoton BMC). At the Global Summit, we demonstrated composite EAT spanning CPU and GPU architectures, enabling a verifier to attest a system without prior knowledge of its hardware configuration.
Hierarchical Hardware Management
Modular cloud infrastructure and bare-metal services are reshaping system management. There is a need for diagnostics and direct control over hardware at scale, while independently securing control-plane management, recovery, and infrastructure connectivity.
Two trends drive this change; in bare-metal instances, control of the host software stack increases the need to manage and understand the underlying hardware subsystems. At the same time, AI and compute platforms are becoming highly disaggregated across boards, chassis, accelerators, and configurable hardware partitions.
Traditional servers rely on a single Baseboard Management Controller (BMC) for diagnostics, recovery, and hardware debug, and do not easily scale to modular, multi-board, and multi-chassis systems. Modern platforms instead require a hierarchy in which Satellite Management Controllers (SMCs) provide local management and aggregate capabilities to a system BMC. The same model supports composable architectures, where socket-level and sub-socket partitioning create additional management domains and interconnects.
The Open Boot and Management Framework (OBMF), an open standards initiative within the Open Compute Project, modernizes connectivity for these architectures. It consolidates interfaces such as SPI, LPC, eSPI, UART, and SMBus over a single USB transport that enables protocol discovery and enumeration. This common interconnect foundation raises the next question: how should management responsibilities be divided across a disaggregated server?
At Open Compute, we demonstrated a hierarchical management topology for bare-metal systems. A system-level BMC manages the system hardware domain, while a separate isolated control plane management domain manages connectivity, for example; a SmartNIC with integrated BMC, or separate rack management appliance. This creates a clear boundary between system management and control plane hardware management. This also allows control of plane management subsystems orchestrated system recovery and management of submodule system boards. For example, during bare-metal system rotation, the control plane can orchestrate transitions where the system BMC is recovered to a known state through USB streaming-boot or, as an interim mechanism, USB Device Firmware Update (DFU).
Figure 5 Hierarchical Hardware Management
The next step in the standardization of the OBMF and hierarchical management architecture in OCP is to define open API contracts between the management domains. This will be part of the DPU abstraction layer project announced at the Open Compute Project Global Summit. The contracts must specify which capabilities are shared from the system domain to the control plane, for operators to ensure reliability, availability and serviceability, without weakening security isolation across domains. Clear interfaces will make hierarchical management scalable, interoperable, and secure across the next generation of cloud and AI infrastructure.
Conventional hardware designs typically boot CPUs, GPUs, and add-in cards from nearby SPI Flash or non-volatile media within the device. This model reflects the historical design of components as semi-discrete units that rely on firmware storage for security and dependency isolation. However, distributing firmware across device-specific stores creates silos that complicate system monitoring, update, and recovery.
Manufacturers commonly use dual A/B flash images to improve resilience, but additional copies do not remove the underlying risk. Bit corruption, operational errors, firmware vulnerabilities, or compromised signing keys can affect both images and leave hardware unrecoverable without physical intervention. The method of adding more recovery images adds redundancy but does not meaningfully improve recovery or mitigate the risk of a persistence attack.
Figure 6 Firmware Flash Silos
In 2022, Microsoft worked with the Open Compute Project community to develop streaming-boot. Instead of storing firmware images on flash alongside every device, streaming-boot delivers firmware over interfaces such as I3C, USB, or PCIe. This method of boot enables flashless devices and replaces custom device-local recovery flows with a unified boot and recovery architecture.
Streaming-boot provides several important capabilities:
- An assume-breach design, the recovery-first architecture is designed to mitigate persistent denial-of-service attacks.
- Reduced dependence on device-local non-volatile firmware storage and the persistence risks it introduces (i.e corruptible state, persist malware, etc).
- Modular firmware delivery using standard protocols and interfaces, including SPDM, PLDM, I3C, and USB.
- Consistent recovery-first workflows across boot and update paths.
- Complement secure boot and attestation flows, with authentication and measurement performed in device isolated memory.
Streaming-boot removes the need for device side non-volatile firmware storage and uses the OBMF transport. It is also a default Caliptra capability, embedding recovery-oriented boot in devices that use the Caliptra root-of-trust security subsystem. At the Open Compute Global Summit, we demonstrate Calitpra streaming boot over USB.
Figure 7 Streaming-boot flow
In the fully resilient streaming-boot architecture, the BMC presents a final challenge because it sits at the bottom of the management and recovery chain. A Caliptra extension addresses this with a network boot processor peripheral that sits outside of the root-of-trust boundary. The processor boots from its own ROM and downloads firmware into isolated SRAM. Caliptra treats the SRAM as an untrusted source, copies the firmware into protected memory, then authenticates and measures it before any execution.
Together, these capabilities move firmware resilience beyond redundant flash images. They establish a recovery-first architecture designed for continuous updates, with unified servicing and recovery paths across the platform.
Caliptra 2.2: Expanding Connectivity and Hardening Security
Caliptra is an open-source silicon Root of Trust that provides identity, attestation, secure boot, key management, and other low-level security services within modern SoCs. Version 2.2 expands Caliptra’s interconnects, optimizes crypto engine area, while adding new hardware security controls.
Caliptra 2.2 adds native multi-device USB support through a new hub and controller block. This interconnect improves SoC streaming boot performance and integrates naturally into modern system management architectures. Alongside I3C and other supported interfaces, USB gives designers greater flexibility in how firmware is loaded and management services are delivered across modular systems.
Caliptra 2.2 reduces the implementation area of the Adams Bridge post-quantum cryptography engine by 50% while delivering a fully masked design. This update also adds Dual Core Lock Step (DCLS), control-flow monitoring, and hardened platform configuration registers.
Together, these improvements extend Caliptra from a silicon root-of-trust into a broader security subsystem for modern cloud and AI infrastructure. Native USB strengthens integration with streaming boot and hierarchical systems management, while additional silicon hardening reinforces secure boot, recovery, identity, and attestation.
Figure 8 Caliptra Subsystem 2.2
Together, these innovations advance a security architecture built for modern cloud and AI infrastructure. Tessera Integrated HSM brings strong isolation to key management; Platform Integrated TPM and composite EAT provide continuous, system-wide measurement; hierarchical management scales partitionable control across disaggregated systems; and streaming-boot establishes recovery as a core platform capability. Caliptra 2.2 ties these advances together with broader connectivity, post-quantum cryptography, and deeper silicon hardening. The result is an open, interoperable foundation that puts isolation, attestation, scalable management, recovery, resilience, and security hardening at the forefront of a modern system design.
Microsoft