Powering Azure infrastructure from grid to chip

As AI infrastructure scales, power availability is increasingly setting the ceiling on how much compute we can deploy.

With workloads evolving towards long-context reasoning and memory-intensive agentic tasks, the power envelope of operating AI at scale has changed dramatically. High density AI systems built with the latest cutting-edge GPUs and AI accelerators are fundamentally changing the demands placed on power infrastructure. As we build the unified engine for intelligence, our ability to deliver compute at the scale required by Frontier AI today rests on a simple reality: greater intelligence relies on how efficiently energy can be delivered through the infrastructure system. This question of energy efficiency spans far beyond sheer compute: it is a challenge that sits across the entire datacenter stack–from the way silicon, servers, and racks are designed to how datacenters and power grids distribute power across the facility.

Scaling AI fundamentally requires us to rethink the power path

As Microsoft scales AI for the frontier era, we’re rethinking power delivery at every layer of the stack, from the grid to the chip. This requires designing the power path as one complete, interconnected system—bringing together the transmission, distribution, conversion, and delivery of power to create a flywheel of efficiency. When each layer is designed with the others in mind, the infrastructure can respond more effectively to the growing scale, density, and dynamism of AI workloads.

Higher-density AI systems are changing the demands placed on power infrastructure. The challenge is not only delivering more power, but coordinating how it is distributed and converted across the facility and the systems it supports. Unlike conventional workloads, large-scale AI training can create rapid changes in demand and power oscillations. Addressing those dynamics requires utility-aligned requirements, responsive control, and filtering within the rack as part of the broader engineering approach.

These demands are prompting a closer look at higher-voltage distribution and opportunities to simplify the power path. Every conversion stage introduces equipment, control requirements, and potential losses. A systems approach creates an opportunity to connect decisions that have traditionally been made independently, from how power enters the datacenter to how it reaches a rack, a server, and ultimately the silicon.

The goal is not to replace every existing architecture at once. Datacenters differ in age, design, available utility service, and deployment needs. The opportunity is to establish a flexible path forward: one that supports existing infrastructure while creating new options as AI power density continues to increase.

Connecting the system through LVDC

A central element of Microsoft’s approach is advancing 800-volt direct-current, as part of the LVDC (Low Voltage Direct Current) power infrastructure with industry partners through the Open Compute Project (OCP). The vision extends beyond the rack to a connected power architecture reaching from the utility grid toward the silicon. It treats facility power, conversion, distribution, rack design, and compute as parts of one engineering system rather than a chain of isolated components.

At a high level, the distribution approach can include 800 VDC/ ±400 VDC . Aligning datacenter distribution, rack interfaces, and downstream conversion around a common strategy can reduce unnecessary conversion complexity and provide a clearer framework for scaling. It also supports more than one adoption path. Existing facilities can introduce local conversion alongside compute racks, while future datacenters can incorporate DC distribution more directly into their architecture.

800VDC architecture improves sustainability by delivering the same power at lower current, enabling smaller conductors and less copper and thereby reducing the embodied carbon associated with mining, refining, manufacturing, and transportation. It also simplifies the power-delivery chain by reducing intermediate conversion stages, lowering electrical losses and waste heat. Together, these improvements reduce both the Scope 3 footprint of the infrastructure and the operational energy required to power AI at scale. 

This flexibility matters because infrastructure transitions happen over time. Operators need options that account for existing investments as well as new builds. By developing common specifications and interfaces, the industry can enable gradual adoption without losing sight of the longer-term grid-to-chip architecture.

Rethinking datacenter and rack power through disaggregated power conversion

Mt. Diablo is an open standard, disaggregated power rack architecture platform for AI infrastructure co-developed with industry partners. By moving power conversion out of the compute rack, the architecture allows power and compute to scale independently while supporting 800 VDC/ ±400 VDC distribution, redundant power delivery, telemetry, and optional energy storage.

This disaggregated “sidecar” model makes the conversion layer modular, allowing power capacity to evolve with increasingly dense AI systems without impacting the compute rack.

At the datacenter and rack levels, we are exploring complementary approaches to simplify power delivery for AI. This means rethinking where and how power conversion happens. SST research explores moving conversion upstream from medium-voltage AC directly to LVDC distribution, while Mt. Diablo disaggregates power conversion from the compute rack to support scalable DC power delivery for AI systems.

Collectively, they illustrate an evolution from today's AC infrastructure toward DC-native AI datacenters.

The future: Solid-state transformer (SST) enablement and datacenter distribution

Together with partners, we are also exploring a solid-state transformer (SST) architecture that converts medium voltage AC (13.8 to 34.5kV) to 800VDC using intermediate medium to high frequency transformer, for direct distribution to the IT rack. This architecture will improve power distribution efficiency, simplify power architecture by eliminating power conversation steps, and provide better energy management with integrated energy storage systems (ESS). We are developing and validating next-generation solid-state transformer technology with integrated energy storage to improve fault ride-through and power resiliency. The work is progressing from prototype validation toward commercial-scale architectures designed for future datacenter power systems

To enable this architecture, key building blocks are SST, ESS for fault ride through & power smoothing, 800VDC switchboard, solid state circuit breakers for fast fault isolation, busway and tap boxes. This entire eco-system of the products is under development, and active engagement with equipment suppliers and industry partners is key to enabling the equipment needs of this transition.

Reliable operation is equally important. OCP’s Clean Backup Power Initiative is developing technology-agnostic requirements for alternatives to traditional diesel-based backup systems. A resilient grid-to-chip architecture must consider normal operation, transient demand, and continuity during disruptions—not as separate problems, but as related design conditions.

The grid-to-chip story does not stop at the rack. LVDC distribution must connect with server-level conversion and the final delivery of power to the processor. Bringing those layers into the same design conversation helps ensure that upstream infrastructure responds to the actual requirements of the silicon it serves.

As LVDC enters the compute tray through the busbar, the Power Delivery Board (PDB) provides the bridge between rack-level distribution and server-level power conversion. It combines key protection and control functions, including LVDC fusing and hot-swap control (HSC), before converting the incoming LVDC to a lower intermediate bus voltage (IBV) for efficient distribution closer to the processors. This conversion stage represents an important opportunity for innovation. Microsoft is working with partners to advance LVDC-to-DC technologies that can support the efficiency, power density, scalability, and dynamic load requirements of next-generation AI systems. But reaching the compute tray is not the end of the power-delivery journey. As power moves closer to the processor, the same system-level design approach must continue through the board, package, and ultimately to the silicon itself.

Vertical power delivery (VPD) carries this grid-to-chip architecture through that final stretch, extending power delivery from the board into the package and silicon domain. By bringing power conversion and delivery closer to the processor, VPD allows power density, distribution path, silicon requirements, chip package architecture and board design to be considered part of a connected system. The result is a continuous engineering path from facility power and rack conversion to the point where power is ultimately consumed by the compute silicon.

Engineering efficiency across the stack

This is where full-stack co-design becomes tangible. Decisions about voltage, conversion, packaging, board design, and workload behavior can be evaluated together. That shared view can help teams identify constraints earlier and avoid optimizing one layer in ways that create complexity elsewhere.

The objective is not a collection of isolated power innovations, but a coordinated system designed for efficiency, resilience, and scalability. Full-stack co-design creates opportunities to simplify conversion, align controls, and use infrastructure capacity more effectively. It can also make the system easier to evolve because interfaces and requirements are considered across layers rather than negotiated, one component at a time.

Building through open collaboration

No single company can make this transition alone. Scaling new power architectures requires collaboration among utilities, datacenter operators, equipment vendors, silicon designers, and technology partners. Each participant owns a different part of the path, and progress depends on interfaces that allow those parts to work together.

Through OCP, Microsoft is contributing to work on disaggregated power racks, solid-state transformers, DC distribution, clean backup power, and a common interface between hyperscale datacenters and the utility grid. These efforts help establish shared requirements as architectures evolve, giving the ecosystem a common foundation for development and deployment.

Open collaboration also creates room for practical choice. Organizations can adopt the elements that fit their facilities and timelines while maintaining alignment with a broader architecture. Published specifications, reference designs, and interoperable interfaces can help turn individual innovations into repeatable building blocks for the industry.

Powering the next generation of AI infrastructure

Scaling AI requires innovation across the entire infrastructure stack, including the path that powers it. By connecting grid, datacenter, rack, server, and silicon design, Microsoft is working toward a more efficient, resilient, and scalable foundation for Azure AI infrastructure.

As AI continues to reshape the scale and design of infrastructure, the power path must evolve with it. We invite you to learn more about Microsoft’s infrastructure innovations and follow our work with the Open Compute Project as we continue building from the grid to the chip.