Written byRani Borkar, Corporate Vice President, Azure Hardware Systems and Infrastructure
Semiconductor and silicon technology are the basis of digital transformation happening everywhere, across industries and our daily lives, impacting the way we work, learn, and play. The continuous improvement in the performance and power of silicon has been key to enabling this innovation. Here at Microsoft, we’ve empowered our long-standing partners in thesemiconductor industryto embrace Azure’s cloud infrastructure and scale out electronic design automation (EDA). With a new EDA-optimized cloud environment running on Azure, the launch ofSynopsys Cloudmarks a significant milestone for the industry by offering silicon design teams the ability to scale and accelerate their development cycles—transforming chip design the way that the cloud transformed computing.
Increasing flexibility and efficiency in silicon development on Azure
The collective rise in time-to-market pressure caused by the global chip shortage and increasing computational demands have caused chipmakers to seek more flexibility and efficiency in the silicon design process. Migrating chip design to Azure’s optimized infrastructure helps address part of this equation by enabling critical design and verification workloads on the cloud—resulting in faster time-to-results and better quality at a lower cost. With Synopsys Cloud built on Azure, chip designers will now also have access to a new pay-per-use model offering automated provisioning of infrastructure and EDA tools to address the growing demands of silicon design.
This “pay-as-you-go” model is a software as a service (SaaS)-based approach that will reduce barriers for companies of all sizes while enabling greater innovation and value for customers and EDA vendors alike. Using the power of Azure’s workload scaling and virtual machine (VM) selection capabilities, Synopsys Cloud customers will be able to optimize critical EDA workloads—from reducing processing time on verification tasks to saving runtime and enabling faster design convergence on library characterization.